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Bits
Mnemonic
Field Name
15:14
IC15
Interrupt Source
Control 15
13:12
IC14
Interrupt Source
Control 14
11:10
IC13
Interrupt Source
Control 13
9:8
IC12
Interrupt Source
Control 12
7:6
IC11
Interrupt Source
Control 11
⎯
5:4
Reserved
3:2
IC9
Interrupt Source
Control 9
1:0
IC8
Interrupt Source
Control 8
Figure 15.4.3 Interrupt Detection Mode Register 1 (2/2)
Chapter 15 Interrupt Controller
Interrupt Source Control 15 (Initial value: 00, R/W)
These bits specify the active state of DMA[1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 14 (Initial value: 00, R/W)
These bits specify the active state of DMA[0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 13 (Initial value: 00, R/W)
These bits specify the active state of SIO[1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 12 (Initial value: 00, R/W)
These bits specify the active state of SIO[0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 11 (Initial value: 00, R/W)
These bits specify the active state of NAND Flash Controller interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 9 (Initial value: 00, R/W)
These bits specify the active state of external INT[7] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
Interrupt Source Control 8 (Initial value: 00, R/W)
These bits specify the active state of external INT[6] interrupts.
00: Low level active
01: High level active
10: Falling edge active
11: Rising edge active
15-13
Explanation
⎯
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