Pci Bus Arbiter Interrupt Mask Register (Pbamask) 0Xd10C - Toshiba TMPR4925 Manual

10.4.25 PCI Bus Arbiter Interrupt Mask Register (PBAMASK)
This register is only valid when using the on-chip PCI Bus Arbiter.
31
15
Bits Mnemonic Field Name
⎯
31:1 Reserved
0 BMIE Broken Master
Detected Interrupt
Enable
Figure 10.4.25 PCI Bus Arbiter Interrupt Mask Register
Reserved
Reserved
Broken Master Detected Interrupt Enable (Initial value: 0, R/W)
Generates an interrupt when a Broken Master is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
10-53
Chapter 10 PCI Controller
0xD10C
1
Description
⎯
16
: Type
: Initial value
0
BMIE
R/W : Type
0 : Initial value