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22.5.3
SDRAM Interface AC Characteristics
(Tc = 0 ~ 70°C, V
Parameter
SDCLK[3:0] Cycle Time
SDCLK[3:0] High Time
SDCLK[3:0] Low Time
SDCLKIN Skew
ADDR[19:16,14:5],SADDR10 Output delay
SDCS[3:0]* Output delay
RAS* Output delay
CAS* Output delay
WE* Output delay
CKE Output delay
DQM[3:0] Output delay
DATA[31:0] Output delay (H->L, L->H)
DATA[31:0] Output delay (High-Z->Valid)
DATA[31:0] Output delay (Valid->High-Z)
DATA[31:0] Input set-up time
DATA[31:0] input hold time
DATA[31:0] Input set-up time
DATA[31:0] input hold time
An SDRAM bus transaction can complete in no more than two clock cycles when the SDCTR.DA is set to 1.
*1:
An SDRAM bus transaction can complete in no more than two clock cycles when the SDCTR.SWB is set to 1.
*2:
*3:
2 cycle signals.
SDCLK[n]
OUTPUT
INPUT
Figure 22.5.3 Timing Diagrams: Output Signals and When Bypass Mode Input Signals (SDCLK Basis)
SDCLK[n]
SDCLKIN
INPUT
Figure 22.5.4 Timing Diagrams: When Non Bypass Mode Input Signals (SDCLK Basis)
Chapter 22 Electrical Characteristics
= 3.3 V ± 0.3 V, V
CCIO
CCInt
Symbol
Rating
t
CYC_SDCLK
t
HIGH_SDCLK
t
LOW_SDCLK
t
Non bypass mode
BP
t
(*1)
VAL_ADDR1
t
VAL_SDCS
t
(*1)
VAL_RAS
t
(*3)
VAL_CAS
t
(*3)
VAL_WE
t
VAL_CKE
t
(*2)
VAL_DQM
t
(*2)
VAL_DATA1
t
(*2)
VAL_DATA1ZV
t
(*2)
VAL_DATA1VZ
t
Bypass mode
SU_DATA1B
t
Bypass mode
HO_DATA1B
t
Non bypass mode
SU_DATA1NB
t
Non bypass mode
HO_DATA1NB
t
VAL_*
t
_*
t
_*
SU
HO
inputs valid
t
BP
t
_*
t
SU
HO
inputs valid
22-5
= 1.5 V ± 0.1 V, V
= 0 V, CL = 50 pF)
SS
Min.
12.5
3
3
0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
6.0
0.5
1.0
2.0
outputs valid
_*
Max.
Unit
⎯
ns
⎯
ns
⎯
ns
4.0
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
7.5
ns
⎯
ns
⎯
ns
⎯
ns
⎯
ns
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