Toshiba TMPR4925 Manual page 179

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Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer
DMSARn[1:0]
Transfer Setting
DMSAIRn
Size
setting is 0
(DMCCRn.XFSZ)
or greater
1 Byte **
2 Bytes *0
4 Bytes 00
4 / 8 Wods
00
(DMMCR.FIFUM[n]=0)
00
4 / 8 Words
**
(DMMCR.FIFUM[n]=1)
-
16 Words
32 Words
†: 4, 0 or -4 can be specified when Source Burst Inhibit bit (DMCCRn, SBINH) is set.
‡: 4, 0 or -4 can be specified when DestinationBurst Inhibit bit (DMCCRn.DBINH) is set.
8.3.8.2 Burst Transfer During Dual Address Transfer
The DMA Controller has a 32-bit 8-stage FIFO on-chip that is connected to the internal bus (G-
Bus) for Burst transfer during Dual Address transfer. Since this FIFO employs a shifter, it is
possible to perform transfer of any address or data size. Burst transfer is only performed when 4
Words or 8 Words is set by the Transfer Setting Size field (DMCCRn.XFSZ) and the FIFO Use
Enable bit (DMMCRn.FIFUM[n]) of the DMA Master Control Register is set.
According to the SDRAM Controller and External Bus Controller specifications, the DMA
Controller cannot perform Burst transfer that spans across 32 word boundaries. Consequently, if
the address that starts DMA transfer is not a multiple of the transfer setting size (DMCCRn.XFSZ)
(is not aligned), transfer cannot be performed by any of the transfer sizes that were specified by a
Burst transfer. Therefore, it is necessary to divide the transfer into multiple Burst transactions of a
transfer size smaller than the specified transfer size. This division method changes according to
the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA Channel Control
Register and whether or not the address offset relative to the Transfer Setting size
(DMCCRn.XFSZ) is equivalent to the source address and destination address combined.
Figure 8.3.3 shows Dual Address Burst transfer when the Transfer Size Mode bit
(DMCCRn.USEXFSZ) is set to "1", the lower 7 bits of the Transfer Start address for the transfer
source are set to 0x54, the lower 7 bits of the Transfer Start address for the transfer destination are
set to 0x1C, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 Words.
Transfer repeats according to the transfer setting size, regardless of the different address offsets.
However, transfers that span across 32 word boundaries are divided. Since data remains in the on-
chip FIFO when in this mode, it becomes possible to share the on-chip FIFO among multiple
DMA channels.
Example: When the transfer address is 0x0001_0000, the DMA Source Address Register
(DMSARn) is as follows below.
DMSAIRn setting is "0" or greater: 0x0001_0000
DMSAIRn setting is a negative value: 0x0001_0003
DMDARn[1:0]
DMSAIRn
DMDAIRn
setting is a
setting is 0
negative
or greater
value
** **
*1 *0
11 00
11 00
11 00
-
**
** -
Cannot be set (Configuration Error)
Cannot be set (Configuration Error)
Chapter 8 DMA Controller
DMDAIRn
DMSAIRn DMDAIRn
setting is a
negative
value
** **
*1 *0
11 00
11 00
11 4/0/-4
- 4
** -4
8-11
DMCNTRn DMCCRn.
[1:0] REVBYTE
** ** 0
*0 *0 0
00 00 0/1
00 00 0/1
4/-4 ‡ 00 0/1
4 0
**
-4 0