Table 6.1.2 Relationship Among Different Clock Frequencies
Input Clock
MASTERCLK
RF Setting
(MHz)
00
01
20
10
11
Internal Clock
CPUCLK
GBUSCLK
GBUSCLKF
(MHz)
(MHz)
(MHz)
200
80
80
100
40
80
50
20
80
25
10
80
6-4
Chapter 6 Clocks
SDCLK
IMBUSCLK
IMBUSCLKF
[1:0]
(MHz)
(MHz)
(MHz)
40
40
80
20
40
40
10
40
20
5
40
10
External Clock (Output)
SYSCLK (MHz)
PCICLK[2:1],
Boot Configuration
PCICLK_IO
Setting
(MHz)
ADDR[4:3]
11
10
01
00
80
40
26.7
20
40
20
13.3
10
33
20
10
6.7
5
10
5
3.3
2.5