Single Address Single Transfer From Memory To I/O (32-Bit Sram) - Toshiba TMPR4925 Manual

8.5.10

Single Address Single Transfer from Memory to I/O (32-bit SRAM)

SDCLK
CS*
ADDR [19:5]
RAS*
CAS*
WE*
CKE*
OE*
DQM [3:0]
ff
DATA [31:0]
ACK*
DMAREQ[n]
DMAACK[n]
DMADONE*
Figure 8.5.11 Single Address Single Transfer from Memory to I/O
0000
(Single Read of 32-bit Data from 32-bit SDRAM)
8-47
Chapter 8 DMA Controller
0040
0 ff