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11.3.9
Reception Time Out
A Reception time out is detected and the Reception Time Out bit (TOUT) of the DMA/Interrupt
Status Register (SIDISR) is set under the following conditions.
•
Non-DMA transfer mode (SIDICRn.RDE = 0):
When at least 1 Byte of reception data exists in the Receive FIFO and the data reception time for
the 2 frames (2 Bytes) after the last reception has elapsed
•
DMA transfer mode (SIDICRn.RDE = 1):
When the data reception time for the 2 frames (2 Bytes) after the last reception has elapsed
regardless of whether reception data exists in the Receive FIFO
11.3.10 Software Reset
It is necessary to reset the FIFO and perform a software reset in the following situations.
(1) After transmission data is set in FIFO, etc., transmission started but stopped before its completion
(2) An overrun occurred during data reception
Software reset is performed by setting the Software Reset bit (SWRST) of the FIFO Control Register
(SIFCR). This bit automatically returns to "0" after initialization is complete. This bit must be set again
since all SIO registers are initialized by software resets.
Chapter 11 Serial I/O Port
11-10
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