Flow Control Register 0 (Siflcr0) 0Xf314 (Ch. 0) Flow Control Register 1 (Siflcr1) 0Xf414 (Ch. 1) - Toshiba TMPR4925 Manual

11.4.6 Flow Control Register 0 (SIFLCR0)
Flow Control Register 1 (SIFLCR1)
31
15 13 12
0 RCS TES
R/W R/W
0
Bits Mnemonic Field Name
⎯
31:13 Reserved
12 RCS RTS Signal
Control Select
11 TES CTS Signal
Control Select
⎯
10 Reserved
9 RTSSC RTS Software
Control
8 RSDE Serial Data
Reception
Enable
7 TSDE Serial Data
Transmit Enable
⎯
6:5 Reserved
4:1 RTSTL RTS Active
Trigger Level
0 TBRK Break
Transmission
0
11 10 9 8
0 RSDE TSDE
RTSSC
R/W R/W R/W
0 0 1
RTS Control Select (Initial value: 0, R/W)
This field sets the reception flow control using RTS output signals.
0: Disable flow control using RTS signals.
1: Enable flow control using RTS signals.
CTS Control Select (Initial value: 0, R/W)
This field sets the transmission flow control using CTS input signals.
0: Disable flow control using CTS signals.
1: Enable flow control using CTS signals.
RTS Software Control (Initial value: 0, R/W)
This register is used for software control of RTS output signals.
0: Set the RTS signal to Low (can receive data).
1: Sets the RTS signal to High (transmission pause request)
Receive Serial Data Enable (Initial value: 1, R/W)
This is the Serial Data Enable bit. When this bit is cleared, data reception starts
after the start bit is detected. The RTS signal will not become High even if this bit is
cleared.
0: Enable (can receive data)
1: Disable (halt reception)
Transmit Serial Data Enable (Initial value: 1, R/W)
This is the Serial Data Transmission Enable bit. When this bit is cleared, data
transmission starts. When set, transmission stops after completing transmission of
the current frame.
0: Enable (can transmit data)
1: Disable (halt transmission)
RTS Trigger Level (Initial value: 0001, R/W)
The RTS hardware control assert level is set by the reception data stage count of
the Receive FIFO.
0000: Disable setting
0001: 1
:
1111: 15
Break Transmit (Initial value: 0, R/W)
Transmits a break. The TXD signal is Low while TBRK is set to "1".
0: Disable (clear break)
1: Enable (transmit break)
Figure 11.4.6 Flow Control Register
11-21
Chapter 11 Serial I/O Port
0xF314 (Ch. 0)
0xF414 (Ch. 1)
7 6 5 4
0
1
Description
⎯
⎯
⎯
16
: Type
: Initial value
1 0
RTSTL TBRK
R/W R/W : Type
0001 0 : Initial value