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15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT)
31
MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT
[31]
[30]
[29]
[28]
15
14
13
12
MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT
[15]
[14]
[13]
[12]
Bits
Mnemonic
Field Name
Internal Request
31:0
MINT[31:0]
Mask
Figure 15.4.20 Interrupt Request Internal Interrupt Mask Register
15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524
31
MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT
[31]
[30]
[29]
[28]
15
14
13
12
MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT
[15]
[14]
[13]
[12]
Bits
Mnemonic
Field Name
31:0
MEXT[31:0]
External Request
Mask
Figure 15.4.21 Interrupt Request External Interrupt Mask Register
[27]
[26]
[25]
[24]
[23]
R/W
0x0000
11
10
9
8
[11]
[10]
[9]
[8]
[7]
R/W
0x0000
Internal Interrupt Mask (Initial value: 0x0000_0000, R/W)
These bits specify whether to use the corresponding flag bit as an internal interrupt
cause. Interrupt causes are masked when this bit is "0."
0: Mask (Reset)
1: Do not mask
[27]
[26]
[25]
[24]
[23]
R/W
0x0000
11
10
9
8
[11]
[10]
[9]
[8]
[7]
R/W
0x0000
External Interrupt Mask (Initial value: 0x0000_0000, R/W)
These bits specify whether to use the corresponding flag bit as an external interrupt
cause. Interrupt causes are masked when this bit is "0."
0: Mask (reset)
1: Do not mask
15-31
Chapter 15 Interrupt Controller
[22]
[21]
[20]
[19]
7
6
5
4
3
[6]
[5]
[4]
[3]
Explanation
[22]
[21]
[20]
[19]
7
6
5
4
3
[6]
[5]
[4]
[3]
Explanation
0xF520
16
[18]
[17]
[16]
: Type
: Initial value
2
1
0
[2]
[1]
[0]
: Type
: Initial value
16
[18]
[17]
[16]
: Type
: Initial value
2
1
0
[2]
[1]
[0]
: Type
: Initial value
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