Block Diagram - Toshiba TMPR4925 Manual

9.2

Block Diagram

SDRAMC
G-Bus
Interface
G-Bus
Control
I/F Signal
G-Bus
I/FSignal
G-Bus
Note: Address signals for SDRAM are ADDR[19:16], SADDR10, and ADDR[14:5]. Don't use ADDR[15]
for SDRAM.
Channel 0 – 3
Control
Control Register
Circuit
Timing Register
Command/Load
Register
Refresh Counter
Control Signal
EBIF
CG
Figure 9.2.1 Block Diagram of SDRAMC
9-2
Chapter 9 SDRAM Controller
SDCS [3:0]*
CKE
WE*
RAS*
CAS*
DQM [3:0]
RP*
EBIF
ADDR [19:16], SADDR10, ADDR[14:5]
DATA [31:0]
SDCLK[1:0]