Toshiba TMPR4925 Manual page 499

Bits Mnemonic Field Name
RXMSBFIRST
10 RMSB
CHIRXFSPOL
9 RFPL
CHITXFSPOL
8 TFPL
CHIRXEDGE
7 REDG
CHITXEDGE
6 TEDG
CHIFSEDGE
5 FEDG
CHITXFSEDGE
4 TFED
CHICLK2XMODE
3 C2X
CHIRXEN
2 REN
RXMSBFIRST bit (Initial value: 0, R/W)
This bit selects between MSB-first and LSB-first serial data formats for each byte
of the CHI receive data.
0: LSB-first
1: MSB-first
CHIRXFSPOL bit (Initial value: 0, R/W)
This bit selects between positive (active high) or negative (active low) polarity for
the received CHIFS signal pulse. This bit must be properly set in CHI sync master
mode, as well as in CHI sync slave mode; In CHI sync master mode,
CHIRXFSPOL must be equal to CHITXFSPOL.
0: positive polarity for the CHIFS pulse. (the rising edge of the CHIFS pulse is
used to trigger the start of the CHI frame period.)
1: negative polarity for the CHIFS pulse. ( the falling edge of the CHIFS pulse is
used to trigger the start of the CHI frame period.)
CHITXFSPOL bit (Initial value: 0, R/W)
This bit selects between positive (active high) or negative (active low) polarity for
the transmitted CHIFS signal pulse, relevant whenever the CHI Module is
configured as master mode.
0: positive polarity for the CHIFS pulse
1: negative polarity for the CHIFS pulse
CHIRXEDGE bit (Initial value: 0, R/W)
This bit selects whether to use either the rising edge or falling edge of CHICLK to
sample the receive data CHIDIN. CHIDIN must be stable before and after the
specified CHICLK edge.
0: falling edge
1: rising edge
CHITXEDGE bit (Initial value: 0, R/W)
This bit selects whether to use either the rising edge or falling edge of CHICLK to
clock out the transmit data CHIDOUT.
0: falling edge
1: rising edge
CHIFSEDGE bit (Initial value: 0, R/W)
This bit selects whether to use either the rising edge or falling edge of CHICLK to
sample the receive frame sync CHIFS. This bit must be properly set in CHI sync
master mode, as well as in CHI sync slave mode. CHIFS must be stable before
and after the specified CHICLK edge; In CHI sync master mode, CHIFSEDGE
must be equal to inverted CHITXFSEDGE.
0: falling edge
1: rising edge
CHITXFSEDGE (Initial value: 0, R/W)
This bit selects whether to use either the rising edge or falling edge of CHICLK to
clock out the transmit frame sync CHIFS, relevant whenever the CHI Module is
configured as master mode.
0: falling edge
1: rising edge
CHICLK2XMODE bit (Initial value: 0, R/W)
This bit selects between 1x and 2x clock modes.
0: 1x clock mode (CHICLK frequency equals the serial data bit rate)
1: 2x clock mode (CHICLK frequency equals twice the serial data bit rate)
CHIRXEN bit (Initial value: 0, R/W)
This bit is used to enable/disable CHI receive processing in the direct CPU
read/write mode, where the CPU reads the received data through the CHI RX
holding register.
This bit has no effect when RX DMA is enabled.
0: Disable (all received data to not be processed by the CHI module)
1: Enable
Figure 16.4.1 Control Register (CTRLREG) (2/3)
16-19
Chapter 16 CHI Module
Description