Table of Contents
Advertisement
22.3.2
DC Characteristics Except for PCI Interface
Parameter
Low-level input voltage
High-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
(1): PCICLKIO, PCIAD[31:0], C_BE[3:0], PAR, FRAME*, IRDY*, TRDY*, STOP*, ID_SEL, DEVSEL*, REQ[3:0]*, GNT[3:0]*,
PERR*, SERR
(2): All PCI interface except ID SEL.
22.4 Power Circuit for PLL
22.4.1
Recommended Circuit for PLL
Parameter
Resistor
Inductance
Capacitor
VddInt / VddPLL
Note: Reference
(Tc = 0 ~ 70°C, V
CCIO
SYM
Conditions
V
(1)
ILPCI
V
(1)
IHPCI
= −500 µA
V
(2) I
OHPCI
OUT
= 1500 µA
V
(2) I
OLPCI
OUT
I
(1) 0 < V
< V
IHPCI
IN
CCIO
I
ILPCI
C1, C2, C3, R, and L should be placed as
closed to the processor as possible.
TX4925
VddInt
PLL1Vdd_A
PLL1Vss_A
Vss
Symbol
R
L
C1
C2
C3
Figure 22.4.1 Power Circuit for PLL
22-3
Chapter 22 Electrical Characteristics
= 3.3 V ± 0.3 V, V
= 1.5 V ± 0.1 V, V
CCInt
Min.
-0.5
1.8
× 0.9
V
CCIO
⎯
-10
-10
R
L
C1
C2
C3
R
L
AS a Reference Value
5.6
2.2
1
82
10
1.5 ± 0.1
= 0 V)
SS
Max.
Unit
0.9
V
V
+ 0.3
V
CCIO
⎯
V
× 0.1
V
V
CCIO
µA
10
µA
10
Unit
Ω
µH
nF
nF
µF
V
Advertisement
Table of Contents
