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21.2.2
Instruction Register
The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting
either one or both of the test to be performed and the Test Data Register to be accessed. The Data
Register is selected according to the instruction code in Table 21.2.1. Refer to the "64-Bit TX System
RISC TX49/H2 Core Architecture" for more information regarding each instruction.
Table 21.2.1 Bit Configuration of JTAG Instruction Register
Instruction Code
MSB → LSB
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
00000011 (0x03)
00000100 - 00001111
00010000 (0x10)
00010001 - 01111111
10000000 - 11111110
11111111 (0xFF)
Figure 21.2.1 shows the format of the Instruction Register.
7
6
MSB
The instruction code is shifted to the Instruction Register starting from the Least Significant Bit.
TDI
Figure 21.2.2 Shift Direction of the Instruction Register
21.2.3
Boundary Scan Register
The Boundary Scan Register contains a single 356-bit shift register to which all TX4925 I/O signals
except for power supply, TDI, TCK, TDO, TMS, TRST* are connected. TEST* and SCANENB*
cannot be tested, but it is possible for the Shift Register to sample the input. Figure 21.2.3 shows the
bits of the Boundary Scan Register.
355
TDI input is fetched to the Most Significant Bit (MSB) of the Boundary Scan Register and the Least
Significant Bit (LSB) of the Boundary Scan Register is sent from the TDO output.
Table 21.2.2 shows the boundary scan sequence relative to the processor signals. Control cells are omitted
in this table.
Chapter 21 Extended EJTAG Interface
Instruction
EXTEST
SAMPLE/PRELOAD
Reserved
IDCODE
Reserved
HIGHZ
Reserved
Refer to the TX49/H2 Core Architecture Manual
BYPASS
5
4
Figure 21.2.1 Instruction Register
MSB
Refer to TX4925 BSDL file.
Figure 21.2.3 Boundary Scan Register
21-3
Selected Data Register
Boundary Scan Register
Boundary Scan Register
Reserved
Device ID Register
Reserved
Bypass Register
Reserved
Bypass Register
3
2
LSB
1
0
LSB
TDO
0
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