Pdmac Status Register (Pdmstatus) 0Xd214 - Toshiba TMPR4925 Manual

10.4.66 PDMAC Status Register (PDMSTATUS)
31 29 28
Reserved
15 14 13 12
PCIACT ERRINT
Reserved DONEINT
R R R
0 0 0
Bits Mnemonic Field Name
⎯
31:29 Reserved
28:24 FIFOCNT FIFO Hold Count
23:20 FIFOWP FIFO Write
Pointer
19:16 FIFORP FIFO Read
Pointer
⎯
15 Reserved
14 PCIACT PCI Active
13 ERRINT Error Interrupt
Status
12 DONEINT Normal Transfer
Complete
Interrupt Status
11 CHNEN Chain Enable
10 XFRACT Transfer Active
9 ACCMP Abnormal Chain
Completion
8 NCCMP Normal Chain
Completion
7 NTCMP Normal Data
Transfer
Complete
24
FIFOCNT
R
00000
11 10 9 8
CHNEN ACCMP NCCMP NTCMP
XFRACT
R R R R/W1C R/W1C
0 0 0 0
FIFO Valid Entry Count (Initial value: 00000, R)
This field indicates the number of DWORDs written to the FIFO but not yet read. This
is a diagnostic function.
FIFO Write Pointer (Initial value: 0x0, R)
This field indicates the next Write position in the FIFO. This is a diagnostic function.
FIFO Read Pointer (Initial value: 0x0, R)
This field indicates the next Read position in the FIFO. This is a dianostic function.
PCI Active (Initial value: 0, R)
1: The PDMAC is requesting to transfer data to or from the PCI bus of it is currently
transferring data.
0: There is no active request or transfer from the PDMAC for the PCI bus.
Error Interrupt Status (Initial value: 0, R)
Indicates whether to signal an error interrupt.
1: An error interrupt request exists.
0: No error interrupt request exists.
Normal Transfer Complete Interrupt Status (Initial value: 0, R)
Indicates whether a Normal Transfer Complete Interrupt is signaled.
This bit becomes "1" when either the Normal Chain Complete bit (NCCMP) is set and
the Normal Chain Complete Interrupt Enable bit (NCCMPIE) is set, or when the
Normal Data Transfer Complete bit (NTCMP) is set and the Normal Data Transfer
Complete Interrupt Enable bit (NTCMPIE) is set.
1: A Normal Transfer Complete Interrupt request exists.
0: No Normal Transfer Complete Interrupt request exists.
Chain Enable (Initial value: 0, R)
This bit is a copy of the Chain Enable bit in the PDMAC Configuration Register.
Transfer Active (Initial value: 0, R)
This bit is a copy of the Transfer Active bit in the PDMAC Configuration Register.
Abnormal Chain Complete (Initial value: 0, R)
1: Indicates that the Chain transfer ended in an error state. In other words, this
reflects an OR operation of the PDMAC Status Register bits [4:0].
0: Indicates that no error has occurred in the Chain transfer since the previous error
bit was cleared.
Note: Bits [4:0] of the PDMAC Status Register must be cleared in order to clear this
bit.
Normal Chain Complete (Initial value: 0, R/W1C)
1: Indicates that the Chain transfer ended in the Normal state.
0: Indicates that Chain transfer has not ended since this bit was previously cleared.
Normal Data Transfer Complete (Initial value: 0, R/W1C)
1: Indicates that the data transfer specified by the PDMAC Register ended in the
Normal state.
0: Indicates that data transfer has not ended since this bit was previously cleared.
Figure 10.4.66 PDMAC Status Register (1/2)
10-96
Chapter 10 PCI Controller
0xD214
23 20
FIFOWP
R
0x0
7 6 5 4
Reserved
PCIPERR PCISERR
R/W1C R/W1C R/W1C R/W1C R/W1C : Type
0 0
Description
⎯
⎯
19 16
FIFORP
R : Type
0x0 : Initial value
3 2 1 0
PCIERR
CHNERR
DATAERR
0 0 0 0 : Initial value