Toshiba TMPR4925 Manual page 512

16.4.12 CHI Clock Register (CHICLOCK)
31
15
Reserved
Bits Mnemonic Field Name
⎯
31:10 Reserved
9 CDIR CHICLKDIR
8 MCLK CHIMCLKEN
7:0 CDIV[7:0] CHICLKDIV
Reserved
10 9 8
CDIR MCLK
R/W R/W
0 1
CHICLKDIR bit (Initial value: 0, R/W)
This bit controls the direction of the CHICLK pin.
0: input (CHI slave mode)
1: output (CHI master mode)
Note: Please set the same value CHICLKDIR and CHIFSDIR. Each set the
difference value (CHIFSDIR = 1, CHICLKDIR = 0 or CHIFSDIR = 0,
CHICLKDIR = 1) can't recommend
CHIMCLKEN bit (Initial value: 1, R/W)
This bit is used to enable or disable the CHICLK counter and CHICLK clock
generation. This bit controls the direction of the CHICLK pin.
0: disable (halting the clock to the CHI Module in order to reduce power
consumption)
1: enable
CHICLKDIV bit (Initial value: 0000_0000, R/W)
These bits define the divide-modulus for the programmable divider used to generate
CHICLK. The divide-modulus is equal to (CHICLKDIV + 2). (See the following Table
16.4.2.)
Note: CLKDIV less than 1 can't recommend
Figure 16.4.12 CHI Clock Register (CHICLOCK)
Table 16.4.2 CHI Clock Divide
CHICLKDIV[7:0]
2
:
N
:
253
254
16-32
Chapter 16 CHI Module
0xA828
7
CDIV
R/W
00000000
Description
⎯
Divide-modulus
4
:
N+2
:
255
256
16
: Type
: Initial value
0
: Type
: Initial value