Block Diagram - Toshiba TMPR4925 Manual

7.2

Block Diagram

G-Bus
ACEHOLD
Register Address
Boot
Options
Figure 7.2.1 Block Diagram of External Bus Controller
External Bus Controller (EBUSC)
Channel Control
G-Bus I/F
CH0
Decoder
Host I/F Timing
Control
Channel Control
CH7
EBIF Control
EBIF
7-2
Chapter 7 External Bus Controller
Register
Address
Decoder
Timing
Control
Register
Address
Decoder
SYSSP CG
CE*[5:0]
OE*
SWE*
BWE*[3:0]/BE*[3:0]
ACK*/READY
UAE
CARDREG*
CARDDIR*
CARD1CSH/L*,CARD2CSH/L*
CARDIORD*
CARDIOWR*
CARD1WAIT*,CARD2WAIT*
ADDR[19:0]
DATA[31:0]
BUSSPRT*
SYSCLK