Toshiba TMPR4925 Manual page 173

SYSCLK
CE*
ADDR [19:0]
ACE*
OE*/BUSSPRT*
SWE*
BWE*
DATA [31:0]
ACK*
1 cycle
DMAREQ[n]
DMAACK[n]
DMADONE*
Figure 8.3.1 External I/O DMA Transfer (Single Address, Level Request)
8.3.3.2 Dual Address Transfer
If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices
and to external memory is each performed continuously. Each access is the same as normal access
except when the DMAACK[n] signal is asserted.
Please refer to "8.3.8 Dual Address Transfer" for information regarding setting the register.
8.3.3.3 Single Address Transfer (Fly-by DMA)
If the Single Address bit (DMCCRn.SNGAD) is set, either data reading from an external I/O
device and data writing to external memory or data reading from external memory and data
writing to an external I/O device is performed simultaneously. The following conditions must be
met in order to perform Single Address transfer.
•
The data bus widths of the external I/O device and external memory match
•
Data can be input/output to/from the external I/O device and external memory during the
same clock cycle
The Transfer Direction bit (MEMIO) of the DMA Channel Control Register (DMCCRn)
specifies the transfer direction.
•
From memory to an external I/O device (DMCCRn.MEMIO = "1")
External memory Read operation to an address specified by the DMA Source Address
Register (DMSARn) is performed simultaneously to assertion of the DMAACK[n] signal.
1c040
f
8-5
Chapter 8 DMA Controller
00040
00000100