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18.4.2
NAND Flash Memory Mode Control Register (NDFMCR)
31
15
Reserved
Bits
Mnemonic
Field Name
⎯
31:8
Reserved
7
WE
Write Enable
6:5
ECC
ECC Control
4
CE
Chip Enable
⎯
3
Reserved
2
BSPRT
Bus Separate
1
ALE
Address Latch
Enable
0
CLE
Command Latch
Enable
Figure 18.4.2 NAND Flash Memory Mode Control Register (NDFMCR)
Chapter 18 NAND Flash Memory Controller
Reserved
8
7
6
WE
ECC
R/W
R/W
0
0
Write Enable (Initial value: 0, R/W)
This bit enables the data write operation. When you write the data in the NAND
flash memory, this bit must be set one.
0: Inhibit write operation
1: Enable write operation
ECC Control 19 (Initial value: 00, R/W)
These bits control the ECC calculating circuits.
ECC
11: Reset ECC circuits.
00: ECC circuits is disable.
01: ECC circuits is enable.
10: Read ECC data calculated by NDFMC.
Chip Enable (Initial value: 0, R/W)
Enable NAND Flash access. This bit must be set one when access to the NAND
Flash memory.
0: Disable (ND_CE* is high.)
1: Enable (ND_CE* is low.)
Bus Separate (Initial value: 0, R/W)
This bit enables the BUSSPRT* signal during NAND Flash memory access.
0: Disable
1: Enable
Address Latch Enable (Initial value: 0, R/W)
This bit specifies the value of ND_ALE signal.
0: Low
1: High
Command Latch Enable (Initial value: 0, R/W)
This bit specifies the value of ND_CLE signal.
0: Low
1: High
18-6
0xC004
5
4
3
2
CE
ALE
BSPRT
Reserved
R/W
R/W
R/W
R/W
0
0
0
Description
⎯
⎯
16
: Type
: Initial value
1
0
CLE
R/W : Type
0
0
: Initial value
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