Toshiba TMPR4925 Manual page 104

Input/
Clock
Output
MASTERCLK Input Master input clock for the TX4925.
The TX4925 internal clock generator multiplies or
divides MASTERCLK to generate internal clock
pulses.
CPUCLK Internal Clock supplied to the TX49/H2 core.
signal
The PLL in the TX4925 generates CPUCLK by
multiplying MASTERCLK. The value of CCFG.RF
can be used to dynamically change the frequency
ratio of CPUCLK to MASTERCLK.
CCFG.RF[1:0]
LL = 10 times MASTERCLK
LH = 5 times MASTERCLK
HL = 2.5 times MASTERCLK
HH = 1.25 times MASTERCLK
Internal
GBUSCLK Clock supplied to peripheral blocks on the G-Bus.
signal
The PLL in the TX4925 generates GBUSCLK by
multiplying MASTERCLK. The value of CCFG.RF
can be used to dynamically change the frequency
ratio of GBUSCLK to MASTERCLK.
CCFG.RF[1:0]
LL = 4 times MASTERCLK
LH = 2 times MASTERCLK
HL = 1 times MASTERCLK
HH = 1/2 times MASTERCLK
GBUSCLKF Internal Clock supplied to peripheral blocks on the G-Bus.
signal
The PLL in the TX4925 generates GBUSCLKF by
multiplying MASTERCLK by 4.
The frequency of this clock does not vary with the
value of CCFG.RG. It is used for SDRAMC refresh
counting.
IMBUSCLK Internal Clock supplied to peripheral modules on the IM-Bus.
signal
The frequency of IMBUSCLK is half that of
GBUSCLK. In the same way as with GBUSCLK, the
frequency of IMBUSCLK varies with the value of
CCFG.RF.
IMBUSCLKF Internal Clock supplied to peripheral modules on the IM Bus.
signal
The frequency of IMBUSCLKF is half that of
GBUSCLKF. In the same way as with GBUSCLKF,
the frequency of IMBUSCLKF does not vary with the
value of CCFG.RF.
It is used as a SIO baud rate clock or TMR count
clock.
SYSCLK Output System clock output from the TX4925. Used by the
devices connected to the external bus controller
(EBUSC).
Boot configuration signals ADDR[4: 3] can set the
frequency ratio of SYSCLK to GBUSCLK.
ADDR[4:3]
LL: GBUSCLK divided by 4
LH: GBUSCLK divided by 3
HL: GBUSCLK divided by 2
HH: GBUSCLK divided by 1
In the same way as with GBUSCLK, the frequency
of SYSCLK varies with the value of CCFG.RF.
The SYSCLKEN bit of the PCFG register can
disable the output of SYSCLK.
Note:To use SYSCLK to access external devices,
Table 6.1.1 TX4925 Clock Signals (1/2)
Description
the SYSCLK rate must match the EBUSC
channel operating rate. For details, refer to
Section 7.3.8.
6-2
Chapter 6 Clocks
Related Related Registers
Configuration Signals (Refer to Chapters 5
(Refer to Section 3.2)
⎯
⎯
CCFG.RF [1:0]
⎯
CCFG.RF [1:0]
⎯
⎯
CCFG.RF [1:0]
⎯
ADDR[4: 3] CCFG.SYSSP
PCFG.SYSCLKEN
CCFG.RF [1:0]
and 10.)
⎯
⎯
⎯