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(a) DMCCRn.USEXFSZ = "0"
Figure 8.3.2 Non-aligned Single Address Burst Transfer
8.3.8
Dual Address Transfer
This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This
applies to the following DMA transfer modes.
•
External I/O (Dual Address) transfer
•
Internal I/O DMA transfer
•
Memory-Memory Copy transfer
8.3.8.1
Channel Register Settings During Dual Address Transfer
Table 8.3.3 shows restrictions of the Channel Register settings during Dual Address transfer. If
these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit
(CFERR) of the DMA Channel Status Register (DMCSRn) is set, and DMA transfer is not
performed.
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the
transfer setting size is 4 bytes or larger, then a value will be set in the DMA Source Address
Register (DMSARn) that reflects the lower 2 bits. Similarly, if the setting of the DMA Destination
Address Increment Register (DMDAIRn) is negative and the transfer setting size is 4 bytes or
larger, then a value will be set in the DMA Destination Address Register (DMDARn) that reflects
the lower 2 bits.
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DMCCRn.XFSZ = 0x4
8-10
Chapter 8 DMA Controller
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DMCCRn. XFSZ = 0x4
(b) DMCCRn.USEXFSZ = "1"
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