Rtc Register (High) (Rtchi) 0Xf900; Rtc Register (Low) (Rtclo) 0Xf904 - Toshiba TMPR4925 Manual

19.4.1 RTC Register (High) (RTCHI)
31
15 12
Reserved
Bits Mnemonic Field Name
⎯
31:12 Reserved
11:0 RTCHI RTC Register
(High)
19.4.2 RTC Register (Low) (RTCLO)
31
15
Bits Mnemonic Field Name
RTC Register
31:0 RTCLO
(Low)
0xF900
Reserved
11
RTC Register (High) (Initial value: undefined, R)
These bits provide the status of the bit 43 to 32 of RTC counter.
The software must read these bits twice and compare the values to ensure that the
counter is not read while the counter is counting since the CPU clock is not
synchronous with the RTC counter clock. If the two reads do not compare, the
software must read the register again to read the correct counter value.
Figure 19.4.1 RTC Register (High) (RTCHI)
0xF904
RTCLO
R
⎯
RTCLO
R
⎯
RTC Register (Low) (Initial value: undefined, R)
These bits provide the status of the bit 31 to 0 of RTC counter.
The software must read these bits twice and compare the values to ensure that the
counter is not read while the counter is counting since the CPU clock is not
synchronous with the RTC counter clock. If the two reads do not compare, the
software must read the register again to read the correct counter value.
Figure 19.4.2 RTC Register (Low) (RTCLO)
19-4
Chapter 19 Real Time Clock (RTC)
RTCHI
R
⎯
Explanation
⎯
Explanation
16
: Type
: Initial value
0
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value