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Table 7.3.10 Access Mapping (PCMCIA in 16-bit Channel and Big Endian Mode)
Access
Access
Address
Word(1/2)
00
Word{2/2}
Triple byte(1/2)
01
Triple byte(2/2)
Triple byte(1/2)
00
Triple byte(2/2)
Half-Word
10
Half-Word
00
Byte
11
Byte
10
Byte
01
Byte
00
Note: Word access and triple byte access yield 2 separate external cycles.
Table 7.3.11 Access Mapping (PCMCIA in 8-bit Channel and Big Endian Mode)
Access
Access
Address
Word(1/4)
00
Word{2/4}
Word(3/4)
Word{4/4}
Triple byte(1/3)
01
Triple byte(2/3)
Triple byte(3/3)
Triple byte(1/3)
00
Triple byte(2/3)
Triple byte(3/3)
Half-Word(1/2)
10
Half-Word(2/2)
Half-Word(1/2)
00
Half-Word(2/2)
Byte
11
Byte
10
Byte
01
Byte
00
Note: Word access yields 4 separate external cycles.
Triple byte access yields 4 separate external cycles.
Half-word access yields 4 separate external cycles.
7.3.9.7
PCMCIA INT# Support
The TX4925 does not have the PCMCIA INT* signal; it is up to the system designer to
implement it external to the device, if necessary.
CARDnCSH*,
ADDR[1:0]
Port Size
00
16-bit
10
16-bit
00
16-bit
10
16-bit
00
16-bit
10
16-bit
10
16-bit
00
16-bit
10
16-bit
10
16-bit
00
16-bit
00
16-bit
CARDnCSH*,
ADDR[1:0]
Port Size
00
8-bit
01
8-bit
10
8-bit
11
8-bit
01
8-bit
10
8-bit
11
8-bit
00
8-bit
01
8-bit
10
8-bit
10
8-bit
11
8-bit
00
8-bit
01
8-bit
11
8-bit
10
8-bit
01
8-bit
00
8-bit
7-23
Chapter 7 External Bus Controller
DATA[15:8]
CARDnCSL*
LL
R[31:24]
LL
R[15:8]
LL
R[31:24]
LH
R[15:8]
HL
-
LL
R[15:8]
LL
R[15:8]
LL
R[15:8]
HL
-
LH
R[7:0]
HL
-
LH
R[7:0]
DATA[15:8]
CARDnCSL*
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
HL
-
DATA[7:0]
R[23:16]
R[7:0]
R[23:16]
-
R[23:16]
R[7:0]
R[7:0]
R[7:0]
R[7:0]
-
R[7:0]
-
DATA[7:0]
R[31:24]
R[23:16]
R[15:8]
R[7:0]
R[23:16]
R[15:8]
R[7:0]
R[31:24]
R[23:16]
R[15:8]
R[15:8]
R[7:0]
R[15:8]
R[7:0]
R[7:0]
R[7:0]
R[7:0]
R[7:0]
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