Timing Diagrams; Command And Address Cycle - Toshiba TMPR4925 Manual

18.5 Timing Diagrams

18.5.1

Command and Address Cycle

Figure 18.5.1 Command and Address Cycle (NDFMCR.BSPRT = 0)
Chapter 18 NAND Flash Memory Controller
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NDFMCR.ALE = 0
NDFSPR.HOLD
NDFSPR.SPW
NDFMCR.CLE = 0
NDFMCR.ALE = 1
NDFMCR.CLE = 1
NDFMCR.CE = 1