External Ack Mode Access (32-Bit Bus) - Toshiba TMPR4925 Manual

7.5.9

External ACK Mode Access (32-bit Bus)

SYSCLK
CE*
ADDR[19:0]
UAE
OE*/BUSSPRT*
SWE*
BWE*
BE*
f
DATA[31:0]
ACK*
Note 1: The TX4925 sets the ACK* signal to High Impedance in the S1 State.
Note 2: External devices drive the ACK* signal to Low (assert the signal) until the ES1
State.
Note 3: External devices drive the ACK* signal to High (deassert the signal) in the ES2
State. If an external device is late in asserting ACK*, then the Wait State is inserted
for the amount of time the external device is late. If a certain condition is met, it is
okay for the ACK* signal to be driven to Low for 1 clock cycle or more. See "7.3.7.4
ACK* Input Timing (External ACK Mode)" for more information.
Figure 7.5.23 1-word Single Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus)
SYSCLK
CE*
ADDR[19:0]
UAE
OE*
BUSSPRT*
SWE*
BWE*
BE*
f
DATA[31:0]
ACK*
Figure 7.5.24 1-word Single Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus)
S1 ES1 ES2
f
S1 ES1
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Chapter 7 External Bus Controller
ES3
S2
0
0
ES2 S2 S3
f
0
S3
f
f
f