Table of Contents
Advertisement
9.3.2.2
Address Signal Mapping (32-bit Data Bus)
Table 9.3.2 shows the address signal mapping when using a 32-bit data bus. B0 is used in the
bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection
in memory with a four-bank configuration. Bits with the description "L/H" output High when
performing auto-precharging, or output Low when not performing auto-precharging.
Table 9.3.2 Address Signal Mapping (32-bit Data Bus) (1/2)
Row address width = 11
Column address width = 8
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column Address
21
22
Row Address
21
22
Row Address Width = 11
Column Address Width = 9
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column Address
22
22
Row Address
22
22
Row Address Width = 11
Column Address Width = 10
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column Address
23
22
Row Address
23
22
Row Address Width = 12
Column Address Width = 8
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column Address
22
23
Row Address
22
23
Row Address Width = 12
Column Address Width = 9
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column Address
23
24
Row Address
23
24
Row Address Width = 12
Column Address Width = 10
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column Address
24
25
Row Address
24
25
SAD
17
16
DR10
14
13
(AP)
22
21
L/H
22
21
22
21
20
19
18
SAD
17
16
DR10
14
13
(AP)
22
21
L/H
22
21
22
21
20
19
18
SAD
17
16
DR10
14
13
(AP)
22
21
L/H
22
21
22
21
20
19
18
SAD
17
16
DR10
14
13
(AP)
22
21
L/H
23
22
22
21
20
19
18
SAD
17
16
DR10
14
13
(AP)
22
21
L/H
23
22
22
21
20
19
18
SAD
17
16
DR10
14
13
(AP)
22
21
L/H
23
22
22
21
20
19
18
9-5
Chapter 9 SDRAM Controller
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
Advertisement
Table of Contents
