Transfer Format - Toshiba TMPR4925 Manual

17.3.4

Transfer Format

During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received serially
(shifted in serially). The serial clock synchronizes shifting and sampling of the information on the two
serial data lines.
The transfer format depends on the setting of the SPHA and SPOL bits in the SPI Control Register 0
(SPCR0). SPHA switches between two fundamentally different protocols, which are described below.
17.3.4.1 SPHA Equals 0 Format
Figure 17.3.1 shows the transfer format for a SPHA=0 transfer.
1
SPICLK
(SPOL=0)
SPICLK
(SPOL=1)
MSB
SPIIN
SPIOUT MSB
Sample Point
In this transfer format, the bit value is captured on the first clock edge. This will be on a rising
edge when SPOL bit equals zero and on a falling edge when SPOL equals one. The value on the
SPIIN and SPIOUT signals changes with the second clock edge on SPICLK. This clock edge will
be a falling edge when SPOL equals zero and a rising edge, when SPOL equals one. With SPOL
equal to zero, the shift clock will be idle low. With SPOL equals 1 it will idle high.
Chapter 17 Serial Peripheral Interface
2 3 4
B6 B5 B4
B6 B5 B4
Figure 17.3.1 Transfer format when SPHA is "0".
17-5
5 6 7
B3 B2 B1
B3 B2 B1
8
LSB
LSB