Toshiba TMPR4925 Manual page 64

Signal Name Type
REQ[3:2]* Input Request
Signals used by the master to request bus mastership.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus
arbiter is used.
In internal arbiter mode, REQ[3:2]* are PCI bus request input signals.
In external arbiter mode, REQ[3:2]* are not used. Because the pins are still placed in the
input state, they must be pulled up externally.
REQ[1]* Input/output/ Request
/INTOUT OD
Signal used by the master to request bus mastership.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus
arbiter is used.
In internal arbiter mode, this signal is a PCI bus request input signal.
In external arbiter mode, this signal is an external interrupt output signal (INTOUT). Refer
to Section "15.3.7 Interrupt Requests".
REQ[0]* Input/output Request
Signal used by the master to request bus mastership.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus
arbiter is used.
In internal arbiter mode, this signal is a PCI bus request input signal.
In external arbiter mode, this signal is a PCI bus request output signal.
GNT[3:0]* Input/output Grant
Indicates that bus mastership has been granted to the PCI bus master.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus
arbiter is used.
In internal arbiter mode, all of GNT[3:0]* are PCI bus grant output signals.
In external arbiter mode, GNT[0]* is a PCI bus grant input signal. Because GNT[3:1]*
also become input signals, they must be pulled up externally.
PERR* Input/output Data Parity Error
Indicates a data parity error in a bus cycle other than special cycles.
SERR* Input/OD System Error
Indicates an address parity error, a data parity error in a special cycle, or a fatal error.
In host mode, SERR* is an input signal. In satellite mode, SERR* is an open-drain output
signal. The mode is determined by the boot configuration signal on the ADDR[19] pin.
Table 3.1.5 PCI Interface Signals (2/2)
Description
3-6
Chapter 3 Signals
Initial State
Input
Selected by
ADDR[1]
H: Input
L: High-Z
Selected by
ADDR[1]
H: Input
L: High
Selected by
ADDR[1]
H: All High
L: Input
Input
Input