Toshiba TMPR4925 Manual page 119

7.3.6.3 Ready Mode
When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by
Ready input from an external device. Ready input is internally initialized. See Section "7.3.7.5
Ready Input Timing" for more information regarding the operation timing.
When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is
performed to see whether the Ready signal was asserted.
When the number of weight cycles is zero, starts READY check one cycle after CE* is asserted.
In the case except for zero, waits the specified number of cycles and starts READY check.
The Ready mode does not support Burst access by the internal bus.
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY
(Input)
EBCCRn.PWT:WT = 2
Chapter 7 External Bus Controller
Start Ready Check
Figure 7.3.3 Ready Mode
7-11
EBCCRn.SHWT = 0