Satellite Mode Pci Status Register (Pcisstatus) 0Xd088 - Toshiba TMPR4925 Manual

10.4.16 Satellite Mode PCI Status Register (PCISSTATUS)
The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration
Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to
read values from either of these registers.
Note: Read this field in the following procedures. If other procedures are used, incorrect data
may be read.
(1) General procedures
After checking the P2GSTATUS.PMSC bit is set, read the PS field.
(2) Procedures to read at any time
To read PS field directly, but not using the procedures shown above (1), read the PS field
twice consecutively. Use the value if the same value is read.
31
Reserved
15 14 13 12
DPE SSE RMA RTA
R R R R
0 0 0 0
Bits Mnemonic Field Name
⎯
31:26 Reserved
25:24 PS Power State
⎯
23:16 Reserved
15 DPE Detected Parity
Error
14 SSE Signaled System
Error
Received Master
13 RMA
Abort
12 RTA Received Target
Abort
11 STA Signaled Target
Abort
10:9 DT Set DEVSEL
Timing
8 MDPE Data Parity
Detected
⎯
7:0 Reserved
26 25 24
PS
R
00
11 10 9 8
STA DT MDPE
R R R
0 01 0
PowerState (Initial value: 00, R)
This is a shadow register of the PowerState field in the PMCSR Register.
Note: Read this field in the following procedures. If other procedures are used,
incorrect data may be read.
(1) General procedures
After checking the P2GSTATUS.PMSC bit is set, read the PS field.
(2) Procedures to read at any time
To read PS field directly, but not using the procedures shown above (1), read the
PS field twice consecutively. Use the value if the same value is read.
Detected Parity Error (Initial value: 0, R)
This is a shadow register of the PCISTATUS.DPE bit.
Signaled System Error (Initial value: 0, R)
This is a shadow register of the PCISTATUS.SSE bit.
Received Master Abort (Initial value: 0, R)
This is a shadow register of the PCISTATUS.RMA bit.
Received Target Abort (Initial value: 0, R)
This is a shadow register of the PCISTATUS.RTA bit.
Signaled Target Abort (Initial value: 0, R)
This is a shadow register of the PCISTATUS.STA bit.
DEVSEL Timing (Fixed value: 01, R)
This is a shadow register of the PCISTATUS.DT field.
Master Data Parity Error Detected (Initial value: 0, R)
This is a shadow register of the PCISTATUS.MDPE bit.
Figure 10.4.16 Satellite Mode PCI Status Register
10-43
Chapter 10 PCI Controller
0xD088
23
Reserved
7
Reserved
Description
⎯
⎯
⎯
16
: Type
: Initial value
0
: Type
: Initial value