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8.3.6
Memory Fill Transfer Mode
When in the Memory Fill Transfer mode, word data set in the DMA Memory Fill Data Register
(DMMFDR) is written to the data region specified by the DMA Source Address Register (DMSARn).
This data can be used for initializing the memory, etc.
Set the DMA Channel Control Register (DMCCRn) as follows.
•
DMCCRn.EXTRQ = 0: Memory transfer mode
•
DMCCRn.SNGAD = 1: Single Address Transfer
•
DMCCRn.MEMIO = 0: Transfer from I/O to memory
In addition, when in the Memory Fill Transfer mode, it is possible to set the interval for requesting
ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control
Register (DMCCRn).
Refer to "8.3.7 Single Address Transfer" for information regarding the setting of other registers.
8.3.7
Single Address Transfer
This section explains register settings during Single Address transfer (DMCCRn.SNGAD = 1). This
applies to the following DMA Transfer modes.
•
External I/O (Single Address) Transfer
•
Memory Fill Transfer
8.3.7.1
Channel Register Settings During Single Address Transfer
Table 8.3.2 shows restrictions of the Channel Register settings during Single Address transfer. If
these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit
(CFERR) of the DMA Channel Status Register (DMCSRn) is set and DMA transfer is not
performed.
For Burst transfer, +4, 0, or –4 can be set to the DMA Source Address Increment Register
(DMSAIRn). Setting 0 is only possible during transfer from memory to external I/O. A
Configuration Error will result if the value "0" is set during transfer from external I/O to memory
or during Memory Fill transfer.
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the
transfer setting size is 2 bytes or larger, then a value will be set in the DMA Source Address
Register (DMSARn) is as follows below.
•
Transfer setting size: 2bytes, (DMSARn) that reflects the lower 1 bits.
•
Transfer setting size: 4bytes, (DMSARn) that reflects the lower 2 bits.
Chapter 8 DMA Controller
8-8
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