Interrupt Level Register 3 (Irlvl3) 0Xf61C - Toshiba TMPR4925 Manual

15.4.7 Interrupt Level Register 3 (IRLVL3)
31
Reserved
15
Reserved
Bits Mnemonic Field Name
⎯
31:27 Reserved
26:24 IL23 Interrupt Level 23
⎯
23:19 Reserved
18:16 IL22 Interrupt Level 22
⎯
15:11 Reserved
10:8 IL7 Interrupt level 7
⎯
7:3 Reserved
2:0 IL6 Interrupt level 6
27 26 24 23
IL23
R/W
000
11 10 8 7
IL7
R/W
000
Interrupt Level of INT[23] (Initial value: 000, R/W)
These bits specify the interrupt level of TMR[2].
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Interrupt Level of INT[22] (Initial value: 000, R/W)
These bits specify the interrupt level of TMR[1].
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Interrupt Level of INT[7] (Initial value: 000, R/W)
These bits specify the interrupt level of external INT[5] interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Interrupt Level of INT[6] (Initial value: 000, R/W)
These bits specify the interrupt level of external INT[4] interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Figure 15.4.7 Interrupt Level Register 3
15-17
Chapter 15 Interrupt Controller
0xF61C
19
Reserved
3
Reserved
Explanation
⎯
⎯
⎯
⎯
18 16
IL22
R/W : Type
000 : Initial value
2 0
IL6
R/W : Type
000 : Initial value