Interrupt Mask Level Register (Irmsk) 0Xf640 - Toshiba TMPR4925 Manual

15.4.12 Interrupt Mask Level Register (IRMSK)
31
15
Bits Mnemonic Field Name
⎯
31:3 Reserved
Interrupt Mask
2:0 IML
Level
Reserved
Reserved
Interrupt Mask Level (Initial value: 000, R/W)
These bits specify the interrupt mask level. Masks interrupts with a mask level lower
than the set mask level.
000: Interrupt mask level 0 (No interrupts masked)
001: Interrupt mask level 1 (Levels 2-7 enabled)
010: Interrupt mask level 2 (Levels 3-7 enabled)
011: Interrupt mask level 3 (Levels 4-7 enabled)
100: Interrupt mask level 4 (Levels 5-7 enabled)
101: Interrupt mask level 5 (Levels 6-7 enabled)
110: Interrupt mask level 6 (Level 7 enabled)
111: Interrupt mask level 7 (Interrupts disabled)
Figure 15.4.12 Interrupt Mask Register
15-22
Chapter 15 Interrupt Controller
0xF640
3 2
Explanation
⎯
16
: Type
: Initial value
0
IML
R/W : Type
000 : Initial value