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8.4.3
DMA Channel Status Register (DMCSRn)
31
15
Reserved
Bits
Mnemonic
Field Name
31:16
WAITC
Wait Counter
⎯
15:11
Reserved
10
CHNEN
Chain Enable
Transfer Stall
9
STLXFER
Detect
WAITC
R
0x0000
11
10
9
8
CHNEN
XFACT ABCHC NCHNC
STLXFER
R
R/W1C
R
0
0
0
Wait Counter (Initial value: 0x0000, R)
This is a diagnostic function.
I/O DMA transfer mode (DMCCRn.EXTRQ = "1")
This counter is decremented by 1 at each 64 G-Bus cycles. After channel n releases
bus ownership, this counter sets the default (the value that is the detection interval
clock cycle count set by the Transfer Stall Detection Interval field
(DMCCRn.STLTIME) divided by 64). The Transfer Stall Detect bit
(DMCSRn.STLXFER) is set when the interval during which bus ownership is not held
reaches the set clock cycle. The counter is reset to the default and stops counting.
Clearing the Transfer Stall Detect bit (DMCSRn.STLXFER) resumes the count and
starts stall detection.
Memory transfer mode (DMCCRn.EXTRQ = "0")
This counter is decremented by 1 at each G-Bus cycle. After bus ownership is
released, the counter is set to the delay clock cycle count set by the Internal Request
Delay field (DMCCRn.INTRQD). When the counter reaches "0" the count stops and
channel n requests bus ownership.
Chain Enable (Initial value: 0, R)
This value is a copy of the Chain Enable bit (CHNEN) of the DMA Channel Control
Register (DMCCRn).
Stalled Transfer Detect (Initial value: 0, R/W1C)
This bit indicates whether the interval during which bus ownership is not held
exceeds the value set by the Transfer Stall Detect Interval field (DMCCRn.STLTIME)
after bus ownership is released when in the I/O DMA transfer mode.
1: Indicates that the interval during which bus ownership was not held exceeds the
DMCCRn.STLTIME setting.
0: The interval during which bus ownership was not held did not exceed the setting
since this bit was last cleared.
Figure 8.4.3 DMA Channel Status Register (1/2)
8-28
Chapter 8 DMA Controller
0xB01C (ch. 0)
0xB05C (ch. 2)
7
6
5
4
3
EXTDN CFERR CHERR
NTRNFC
R
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type
0
0
0
0
0
Description
⎯
0xB03C (ch. 1)
0xB07C (ch. 3)
16
: Type
: Initial value
2
1
0
DESERR SORERR
0
0
0
: Initial value
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