Single Address Single Transfer From Memory To I/O Of Last Cycle When Dmadone* Signal Is Set To Output - Toshiba TMPR4925 Manual

8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE*
Signal is Set to Output
SDCLK
CS*
ADDR [19:5]
RAS*
CAS*
WE*
CKE*
OE*/BUSSPRT*
DQM [7:0]
ff
DATA [63:0]
ACK*
DMAREQ[n]
DMAACK[n]
DMADONE*
Figure 8.5.13 Single Address Single Transfer from Memory to I/O
0000
(Single Read of 64-bit Data from 64-bit SDRAM)
8-49
Chapter 8 DMA Controller
0041
00 ff