Table of Contents
Advertisement
Source Address
32
0
50
54
58
5c
60
64
68
6c
70
74
78
7c
00
04
08
0c
10
14
18
1c
(a) Address offset is equivalent
32
0
50
54
58
5c
60
64
68
6c
70
74
78
7c
00
04
08
1c
10
14
18
1c
20
24
28
2c
30
(b) Address offset differs
Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0)
Chapter 8 DMA Controller
FIFO (8 Double Words)
8-14
Destination Address
32
0
10
14
18
1c
20
24
28
2c
30
34
38
3c
40
44
48
4c
50
54
58
5c
32
0
10
14
18
1c
20
24
28
2c
30
34
38
3c
40
44
48
4c
50
54
58
5c
60
64
68
6c
70
Advertisement
Table of Contents
