Interrupt Level Register 2 (Irlvl2) 0Xf618 - Toshiba TMPR4925 Manual

15.4.6 Interrupt Level Register 2 (IRLVL2)
31
Reserved
15
Reserved
Bits Mnemonic Field Name
⎯
31:11 Reserved
26:24 IL21 Interrupt Level 21
⎯
23:19 Reserved
18:16 IL20 Interrupt Level 20
⎯
15:11 Reserved
10:8 IL5 Interrupt Level 5
⎯
7:3 Reserved
2:0 IL4 Interrupt Level 4
IL21
R/W
000
11 10 8 7
IL5
R/W
000
Interrupt Level of INT[21] (Initial value: 000, R/W)
These bits specify the interrupt level of TMR[0].
000: Interrupt Level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Interrupt Level of INT[20] (Initial value: 000, R/W)
These bits specify the interrupt level of PCIC interrupts.
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Interrupt Level of INT[5] (Initial value: 000, R/W)
These bits specify the interrupt level of external INT[3].
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Interrupt Level of INT[4] (Initial value: 000, R/W)
These bits specify the interrupt level of external INT[2].
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
Figure 15.4.6 Interrupt Level Register 2
15-16
Chapter 15 Interrupt Controller
0xF618
Reserved
3
Reserved
Explanation
⎯
⎯
⎯
⎯
16
IL20
R/W : Type
000 : Initial value
2 0
IL4
R/W : Type
000 : Initial value