P2G Interrupt Mask Register (P2Gmask) 0Xd098 - Toshiba TMPR4925 Manual

10.4.20 P2G Interrupt Mask Register (P2GMASK)
31
15
Bits Mnemonic Field Name
⎯
31:3 Reserved
2 PMSCIE Power
Management
State Change
Interrupt Enable
1 PERRIE PERR* Detect
Interrupt Enable
0 GBEIE G-Bus Bus Error
Detect Interrupt
Enable
Reserved
Reserved
Power Management State Change Interrupt Enable (Initial value: 0, R/W)
Generates an interrupt when the PowerState field of the Power Management Register
(PMCSR) is rewritten.
1: Generates an interrupt.
0: Does not generate an interrupt.
PERR* Interrupt Enable (Initial value: 0, R/W)
This bit generates an interrupt when the Parity Error signal (PERR*) is asserted.
1: Generates an interrupt.
0: Does not generate an interrupt.
G-Bus Bus Error Interrupt Enable (Initial value: 0, R/W)
This bit generates an interrupt when a Bus Error is asserted while the PCI Controller
is the G-Bus Master. (Target cycle to G-Bus)
1: Generates an interrupt.
0: Does not generate an interrupt.
Figure 10.4.20 P2G Interrupt Mask Register
10-47
Chapter 10 PCI Controller
0xD098
3 2 1
PMSCIE PERRIE
R/W R/W
0 0
Description
⎯
16
: Type
: Initial value
0
GBEIE
R/W : Type
0 : Initial value