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Manuals and User Guides for Toshiba TMPR4925. We have
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Toshiba TMPR4925 manual available for free PDF download: Manual
Toshiba TMPR4925 Manual (590 pages)
64-Bit TX System RISC TX49 Family
Brand:
Toshiba
| Category:
Computer Hardware
| Size: 3.14 MB
Table of Contents
Table of Contents
5
Safety Precautions
19
Absolute Maximum Ratings
28
Unused Pins
28
Safety Standards
32
Features
47
Outline
47
TX49/H2 Processor Core Features
48
TX4925 Peripheral Circuit Features
49
Block Diagram
55
TX4925 Block Diagram
55
Signals
59
Pin Signal Description
59
Signals Common to SDRAM and External Bus Interfaces
59
SDRAM Interface Signals
60
External Interface Signals
61
DMA Interface Signals
63
PCI Interface Signals
63
Serial I/O Interface Signals
65
Timer Interface Signals
65
Parallel I/O Interface Signals
65
AC-Link Interface Signals
66
Interrupt Signals
66
CHI Interface Signals
66
SPI Interface Signals
67
NAND Flash Memory Interface Signals
67
Extended EJTAG Interface Signals
67
Clock Signals
68
Initialization Signals
68
Test Signals
69
Power Supply Pins
69
Boot Configuration
70
Pin Multiplexing
73
Address Mapping
77
TX4925 Physical Address Map
77
Register Map
78
Addressing
78
Ways to Access to Internal Registers
78
Register Map
79
Configuration Register
89
Outline
89
Detecting G-Bus Timeout
89
Register
90
Chip Configuration Register (CCFG) 0Xe000
91
Chip Revision ID Register (REVID) 0Xe004
93
Pin Configuration Register (PCFG) 0Xe008
94
Timeout Error Access Address Register (TOEA) 0Xe00C
96
Power down Control Register (PDNCTR) 0Xe010
97
GBUS Arbiter Priority Register (GARBP) 0Xe018
98
Timeout Count Register (TOCNT) 0Xe020
98
DMA Request Control Register (DRQCTR) 0Xe024
99
Clock Control Register (CLKCTR) 0Xe028
100
GBUS Arbiter Control Register (GARBC) 0Xe02C
102
Register Address Mapping Register (RAMP) 0Xe030
102
Clocks
103
TX4925 Clock Signals
103
Power-Down Mode
107
Halt Mode and Doze Mode
107
Power Reduction for Peripheral Modules
107
Power-On Sequence
108
External Bus Controller
109
Features
109
Block Diagram
110
Detailed Explanation
111
External Bus Control Register
111
Global/Boot-Up Options
112
Address Mapping
113
External Address Output
114
Data Bus Size
115
Access Modes
117
Access Timing
121
Clock Options
127
PCMCIA Mode
128
Register
132
External Bus Channel Control Register (Ebccrn) 0X9000 (Ch. 0), 0X9008 (Ch. 1)
133
0X9010 (Ch. 2), 0X9018 (Ch. 3) 0X9020 (Ch. 4), 0X9028 (Ch. 5) 0X9030 (Ch. 6), 0X9038 (Ch. 7)
133
External Bus Base Address Register (Ebbarn) 0X9000 (Ch. 0), 0X9008 (Ch. 1) 0X9010 (Ch. 2), 0X9018 (Ch. 3) 0X9020 (Ch. 4), 0X9028 (Ch. 5) 0X9030 (Ch. 6), 0X9038 (Ch. 7)
136
Timing Diagrams
137
UAE Signal
138
Normal Mode Access (Single, 32-Bit Bus)
140
Normal Mode Access (Burst, 32-Bit Bus)
144
Normal Mode Access (Single, 16-Bit Bus)
146
Normal Mode Access (Burst, 16-Bit Bus)
150
Normal Mode Access (Single, 8-Bit Bus)
152
Normal Mode Access (Burst, 8-Bit Bus)
155
Page Mode Access (Burst, 32-Bit Bus)
157
External ACK Mode Access (32-Bit Bus)
159
READY Mode Access (32-Bit Bus)
165
Flash ROM, SRAM Usage Example
167
DMA Controller
169
Features
169
Block Diagram
170
Detailed Explanation
171
Transfer Mode
171
On-Chip Registers
171
External I/O DMA Transfer Mode
172
Internal I/O DMA Transfer Mode
175
Memory-Memory Copy Mode
175
Memory Fill Transfer Mode
176
Single Address Transfer
176
Dual Address Transfer
178
DMA Transfer
183
Chain DMA Transfer
184
Dynamic Chain Operation
186
Interrupts
187
Transfer Stall Detection Function
187
Arbitration Among DMA Channels
188
Restrictions in Access to PCI Bus
188
Registers
189
DMA Master Control Register (DMMCR) 0Xb0A8
190
0Xb058 (Ch. 2) 0Xb078 (Ch. 3)
192
DMA Channel Status Register (Dmcsrn) 0Xb01C (Ch. 0) 0Xb03C (Ch. 1) 0Xb05C (Ch. 2) 0Xb07C (Ch. 3)
196
0Xb044 (Ch. 2) 0Xb064 (Ch. 3)
198
0Xb048 (Ch. 2) 0Xb068 (Ch. 3)
199
0Xb040 (Ch. 2) 0Xb060 (Ch. 3)
200
DMA Source Address Increment Register (Dmsairn) 0Xb010 (Ch. 0) 0Xb030 (Ch. 1)
201
0Xb050 (Ch. 2) 0Xb070 (Ch. 3)
201
0Xb054 (Ch. 2) 0Xb074 (Ch. 3)
202
0Xb04C (Ch. 2) 0Xb06C (Ch. 3)
203
DMA Memory Fill Data Register (DMMFDR) 0Xb0A4
204
Timing Diagrams
205
Single Address Single Transfer from Memory to I/O (32-Bit ROM)
205
Single Address Single Transfer from Memory to I/O (16-Bit ROM)
206
Single Address Single Transfer from I/O to Memory (32-Bit SRAM)
207
Single Address Burst Transfer from Memory to I/O (32-Bit ROM)
208
Single Address Burst Transfer from I/O to Memory (32-Bit SRAM)
209
Single Address Single Transfer from Memory to I/O (16-Bit ROM)
211
Single Address Single Transfer from I/O to Memory (16-Bit SRAM)
212
Single Address Single Transfer from Memory to I/O (32-Bit Half Speed ROM)
213
Single Address Single Transfer from I/O to Memory (32-Bit Half Speed SRAM)
214
Single Address Single Transfer from Memory to I/O (32-Bit SRAM)
215
Single Address Single Transfer from I/O to Memory (32-Bit SDRAM)
216
Single Address Single Transfer from Memory to I/O of Last Cycle When DMADONE* Signal Is Set to Output
217
Single Address Single Transfer from Memory to I/O (32-Bit SDRAM)
218
Single Address Single Transfer from I/O to Memory (32-Bit SDRAM)
219
External I/O Device - SRAM Dual Address Transfer
220
External I/O Device - SDRAM Dual Address Transfer
222
External I/O Device (Non-Burst) - SDRAM Dual Address Transfer
224
SDRAM Controller
227
Characteristics
227
Block Diagram
228
Detailed Explanation
229
Supported SDRAM Configurations
229
Address Mapping
230
Initialization of SDRAM
235
Low Power Consumption Function
236
Bus Errors
237
Memory Read and Memory Write
237
Slow Write Burst
237
Clock Feedback
238
Registers
238
SDRAM Channel Control Register (SDCCR0) 0X8000 (Ch. 0) (SDCCR1) 0X8004 (Ch. 1) (SDCCR2) 0X8008 (Ch. 2) (SDCCR3) 0X800C (Ch. 3)
239
SDRAM Timing Register (SDCTR) 0X8020
241
SDRAM Command Register (SDCCMD) 0X802C
243
Timing Diagrams
244
Single Read (32-Bit Bus)
244
Single Write (32-Bit Bus)
246
Burst Read (32-Bit Bus)
248
Burst Write (32-Bit Bus)
249
Burst Write (32-Bit Bus, Slow Write Burst)
250
Single Read (16-Bit Bus)
251
Single Write (16-Bit Bus)
253
Low Power Consumption and Power down Mode
255
SDRAM Usage Example
259
PCI Controller
261
Features
261
Overall
261
Initiator Function
261
Target Function
261
PCI Arbiter
262
PDMAC (PCI DMA Controller)
262
Block Diagram
263
Detailed Explanation
264
Terminology Explanation
264
On-Chip Register
264
Supported PCI Bus Commands
266
Initiator Access (G-Bus → PCI Bus Address Conversion)
268
Target Access (PCI Bus → G-Bus Address Conversion)
270
Post Write Function
273
Endian Switching Function
273
Power Management
274
PDMAC (PCI DMA Controller)
275
Error Detection, Interrupt Reporting
279
PCI Bus Arbiter
280
PCI Boot
282
Set Configuration Space
283
PCI Clock Signal
283
PCI Controller Control Register
284
ID Register (PCIID) 0Xd000
286
PCI Status, Command Register (PCISTATUS) 0Xd004
287
Class Code, Revision ID Register (PCICCREV) 0Xd008
289
PCI Configuration 1 Register (PCICFG1) 0Xd00C
290
P2G Memory Space 0 PCI Base Address Register (P2GM0PBASE) 0Xd010
291
P2G Memory Space 1 PCI Base Address Register (P2GM1PBASE) 0Xd014
292
P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0Xd018
293
P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0Xd01C
294
Subsystem ID Register (PCISID) 0Xd02C
295
Capabilities Pointer Register (PCICAPPTR) 0Xd034
296
PCI Configuration 2 Register (PCICFG2) 0Xd03C
297
G2P Timeout Count Register (G2PTOCNT) 0Xd040
298
G2P Configuration Register (G2PCFG) 0Xd060
299
G2P Status Register (G2PSTATUS) 0Xd064
301
G2P Interrupt Mask Register (G2PMASK) 0Xd068
302
Satellite Mode PCI Status Register (PCISSTATUS) 0Xd088
303
PCI Status Interrupt Mask Register (PCIMASK) 0Xd08C
304
P2G Configuration Register (P2GCFG) 0Xd090
305
P2G Status Register (P2GSTATUS) 0Xd094
306
P2G Interrupt Mask Register (P2GMASK) 0Xd098
307
P2G Current Command Register (P2GCCMD) 0Xd09C
308
PCI Bus Arbiter Request Port Register (PBAREQPORT) 0Xd100
309
PCI Bus Arbiter Configuration Register (PBACFG) 0Xd104
311
PCI Bus Arbiter Status Register (PBASTATUS) 0Xd108
312
PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0Xd10C
313
PCI Bus Arbiter Broken Master Register (PBABM) 0Xd110
314
PCI Bus Arbiter Current Request Register (PBACREQ) 0Xd114
316
PCI Bus Arbiter Current Grant Register (PBACGNT) 0Xd118
317
PCI Bus Arbiter Current State Register (PBACSTATE) 0Xd11C
318
G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0Xd120
319
G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0Xd128
320
G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0Xd130
321
G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0Xd138
322
G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0Xd140
323
G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0Xd144
324
G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0Xd148
325
G2P I/O Space Address Mask Register (G2PIOMASK) 0Xd14C
326
G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0Xd150
327
G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0Xd158
328
G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0Xd160
329
G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0Xd168
330
PCI Controller Configuration Register (PCICCFG) 0Xd170
331
PCI Controller Status Register (PCICSTATUS) 0Xd174
332
PCI Controller Interrupt Mask Register (PCICMASK) 0Xd178
333
P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0Xd180
334
P2G Memory Space 0 Control Register (P2GM0CTR) 0Xd184
335
P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0Xd188
336
P2G Memory Space 1 Control Register (P2GM1CTR) 0Xd18C
337
P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0Xd190
338
P2G Memory Space 2 Control Register (P2GM2CTR) 0Xd194
339
P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0Xd198
340
P2G I/O Space Control Register (P2GIOCTR) 0Xd19C
341
G2P Configuration Address Register(G2PCFGADRS) 0Xd1A0
342
G2P Configuration Data Register (G2PCFGDATA) 0Xd1A4
343
G2P Interrupt Acknowledge Data Register (G2Pintack)0Xd1C8
344
G2P Special Cycle Data Register (G2PSPC) 0Xd1Cc
345
Configuration Data 0 Register (PCICDATA0) 0Xd1E0
346
Configuration Data 1 Register (PCICDATA1) 0Xd1E4
347
Configuration Data 2 Register (PCICDATA2) 0Xd1E8
348
Configuration Data 3 Register (PCICDATA3) 0Xd1Ec
349
PDMAC Chain Address Register (PDMCA) 0Xd200
350
PDMAC G-Bus Address Register (PDMGA) 0Xd204
351
PDMAC PCI Bus Address Register (PDMPA) 0Xd208
352
PDMAC Count Register (PDMCTR) 0Xd20C
353
PDMAC Configuration Register (PDMCFG) 0Xd210
354
PDMAC Status Register (PDMSTATUS) 0Xd214
356
PCI Configuration Space Register
358
Capability ID Register (Cap_Id) 0Xdc
359
Next Item Pointer Register (Next_Item_Ptr) 0Xdd
360
Power Management Capability Register (PMC) 0Xde
361
Power Management Control/Status Register (PMCSR) 0Xe0
362
Serial I/O Port
363
Features
363
Block Diagram
364
Detailed Explanation
365
Overview
365
Data Format
365
Serial Clock Generator
367
Data Reception
369
Data Transmission
369
DMA Transfer
370
Flow Control
370
Reception Data Status
371
Reception Time out
372
Software Reset
372
Error Detection/Interrupt Signaling
373
Multi-Controller System
374
Registers
375
Line Control Register 0 (SILCR0) 0Xf300 (Ch. 0) Line Control Register 1 (SILCR1) 0Xf400 (Ch. 1)
376
Dma/Interrupt Control Register 0 (SIDICR0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (SIDICR1) 0Xf404 (Ch. 1)
377
Dma/Interrupt Status Register 0 (SIDISR0) 0Xf308 (Ch. 0) Dma/Interrupt Status Register 1 (SIDISR1) 0Xf408 (Ch. 1)
379
Status Change Interrupt Status Register 0 (SISCISR0) 0Xf30C (Ch. 0) Status Change Interrupt Status Register 1 (SISCISR1) 0Xf40C (Ch. 1)
381
FIFO Control Register 0 (SIFCR0) 0Xf310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0Xf410 (Ch. 1)
382
Flow Control Register 0 (SIFLCR0) 0Xf314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0Xf414 (Ch. 1)
383
Transmit FIFO Register 0 (SITFIFO0) 0Xf31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0Xf41C (Ch. 1)
385
Receive FIFO Register 0 (SIRFIFO0) 0Xf320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0Xf420 (Ch. 1)
386
Timer/Counter
387
Features
387
Block Diagram
388
Detailed Explanation
389
Overview
389
Counter Clock
389
Counter
390
Interval Timer Mode
390
Pulse Generator Mode
392
Watchdog Timer Mode
393
Registers
395
Timer Control Register N (Tmtcrn) TMTCR0 0Xf000 TMTCR1 0Xf100 TMTCR2 0Xf200
396
Timer Interrupt Status Register N (Tmtisrn) TMTISR0 0Xf004 TMTISR1 0Xf104 TMTISR2 0Xf204
397
TMITMR2 0Xf210
400
Pulse Generator Mode Register N (Tmpgmrn) TMPGMR0 0Xf030 TMPGMR1 0Xf130
402
Watchdog Timer Mode Register N (Tmwtmrn) TMWTMR2 0Xf240
403
TMTRR2 0Xf2F0
404
Parallel I/O Port
405
Characteristics
405
Block Diagram
405
Detailed Description
406
Selecting PIO Pins
406
General-Purpose Parallel Port
406
Registers
406
PIO Output Data Register (PIODO) 0Xf500
407
PIO Input Data Register (PIODI) 0Xf504
407
PIO Direction Control Register (PIODIR) 0Xf508
408
PIO Open Drain Control Register (PIOOD) 0Xf50C
408
AC-Link Controller
409
Features
409
Configuration
410
Functional Description
411
CODEC Connection
411
Pin Configuration
412
Usage Flow
413
AC-Link Start up
415
CODEC Register Access
416
Sample-Data Transmission and Reception
417
GPIO Operation
422
Interrupt
423
AC-Link Low-Power Mode
423
Registers
424
ACLC Control Enable Register (ACCTLEN) 0Xf700
425
ACLC Control Disable Register (ACCTLDIS) 0Xf704
428
ACLC CODEC Register Access Register (ACREGACC) 0Xf708
430
ACLC Interrupt Status Register (ACINTSTS) 0Xf710
431
ACLC Interrupt Masked Status Register (ACINTMSTS) 0Xf714
433
ACLC Semaphore Register (ACSEMAPH) 0Xf720
434
ACLC GPI Data Register (ACGPIDAT) 0Xf740
435
ACLC GPO Data Register (ACGPODAT) 0Xf744
436
ACLC Slot Enable Register (ACSLTEN) 0Xf748
437
ACLC Slot Disable Register (ACSLTDIS) 0Xf74C
439
ACLC FIFO Status Register (ACFIFOSTS) 0Xf750
440
ACLC DMA Request Status Register (ACDMASTS) 0Xf780
442
ACLC DMA Channel Selection Register (ACDMASEL) 0Xf784
443
ACLC Surround Data Register (ACAUDODAT)
444
ACLC Modem Output Data Register (ACAUDIDAT) 0Xf7B0
446
ACLC Modem Input Data Register (ACMODIDAT) 0Xf7Bc
447
ACLC Revision ID Register (ACREVID) 0Xf7Fc
448
Interrupt Controller
449
Characteristics
449
Block Diagram
450
Detailed Explanation
452
Interrupt Sources
452
Interrupt Request Detection
453
Interrupt Level Assigning
453
Interrupt Priority Assigning
453
Interrupt Notification
454
Clearing Interrupt Requests
455
Interrupt Requests
455
Registers
456
Interrupt Detection Enable Register (IRDEN) 0Xf600
457
Interrupt Detection Mode Register 0 (IRDM0) 0Xf604
458
Interrupt Detection Mode Register 1 (IRDM1) 0Xf608
460
Interrupt Level Register 0 (IRLVL0) 0Xf610
462
Interrupt Level Register 1 (IRLVL1) 0Xf614
463
Interrupt Level Register 2 (IRLVL2) 0Xf618
464
Interrupt Level Register 3 (IRLVL3) 0Xf61C
465
Interrupt Level Register 4 (IRLVL4) 0Xf620
466
Interrupt Level Register 5 (IRLVL5) 0Xf624
467
Interrupt Level Register 6 (IRLVL6) 0Xf628
468
Interrupt Level Register 7 (IRLVL7) 0Xf62C
469
Interrupt Mask Level Register (IRMSK) 0Xf640
470
Interrupt Edge Detection Clear Register (IREDC) 0Xf660
471
Interrupt Current Status Register (IRCS) 0Xf6A0
475
Interrupt Request Flag Register 0 (IRFLAG0) 0Xf510
477
Interrupt Request Flag Register 1 (IRFLAG1) 0Xf514
477
Interrupt Request Polarity Control Register (IRPOL) 0Xf518
478
Interrupt Request Control Register (IRRCNT) 0Xf51C
478
Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0Xf520
479
Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0Xf524
479
CHI Module
481
Characteristics
481
Block Diagram
482
Detailed Explanation
483
Transmitter
483
Receiver
484
Clock and Control Generation
484
DMA Address Generation
486
Timing Diagram
488
Interrupts
489
Frame Structure and Serial Timing
490
Configurations
496
Registers
497
CHI Control Register (CTRL) 0Xa800
498
CHI Pointer Enable Register (PNTREN) 0Xa804
501
CHI Receive Pointer a Register (RXPTRA) 0Xa808
503
CHI Receive Pointer B Register (RXPTRB) 0Xa80C
504
CHI Transmit Pointer a Register (TXPTRA) 0Xa810
505
CHI Transmit Pointer B Register (TXPTRB) 0Xa814
506
CHI SIZE Register (CHISIZE) 0Xa818
507
CHI RX Start Register (RXSTRT) 0Xa81C
508
CHI TX Start Register (TXSTRT) 0Xa820
509
CHI TX Holding Register (CHIHOLD) 0Xa824
510
CHI RX Holding Register (CHIHOLD) 0Xa824
511
HI Interrupt Enable Register (CHIINTE) 0Xa82C
513
CHI Interrupt Status Register (CHIINT) 0Xa830
514
Serial Peripheral Interface
515
Characteristics
515
Block Diagram
516
Detailed Explanation
517
Operation Mode
517
Transmitter/Receiver
517
Baud Rate Generator
518
Transfer Format
519
Inter Frame Space Counter
520
SPI Buffer Structure
521
SPI System Errors
521
Interrupts
521
Registers
522
SPI Master Control Register (SPMCR) 0Xf800
523
SPI Control Register 0 (SPCR0) 0Xf804
524
SPI Control Register 1 (SPCR1) 0Xf808
524
SPI Inter Frame Space Register (SPFS) 0Xf80C
527
SPI Status Register (SPSR) 0Xf814
528
SPI Data Register (SPDR) 0Xf818
530
NAND Flash Memory Controller
531
Characteristics
531
Block Diagram
531
Detailed Explanation
532
Access to NAND Flash Memory
532
ECC Control
534
Registers
535
NAND Flash Memory Data Transfer Register (NDFDTR) 0Xc000
535
NAND Flash Memory Mode Control Register (NDFMCR) 0Xc004
536
NAND Flash Memory Status Register (NDFSR) 0Xc008
537
NAND Flash Memory Interrupt Status Register (NDFISR) 0Xc00C
538
NAND Flash Memory Interrupt Mask Register (NDFIMR) 0Xc010
539
NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0Xc014
540
NAND Flash Memory Reset Register (NDFRSTR) 0Xc018
541
Timing Diagrams
542
Command and Address Cycle
542
Data Read Cycle
543
Data Write Cycle
545
Example of Using NAND Flash Memory
546
Real Time Clock (RTC)
547
Features
547
Block Diagrams
548
Operations
549
Operation
549
Interrupt
549
Registers
549
RTC Register (High) (RTCHI) 0Xf900
550
RTC Register (Low) (RTCLO) 0Xf904
550
Alarm Register (High) (ALARMHI) 0Xf908
551
Alarm Register (Low) (ALARMLO) 0Xf90C
551
RTC Control Register (RTCCTRL) 0Xf910
552
RTC Interrupt Status Register (RTCINT) 0Xf914
553
Removed
555
Extended EJTAG Interface
557
JTAG Boundary Scan Test
558
JTAG Controller and Register
558
Instruction Register
559
Boundary Scan Register
559
Device ID Register
562
Initializing the Extended EJTAG Interface
563
Electrical Characteristics
565
Absolute Maximum Rating
565
Recommended Operating Conditions
565
DC Characteristics
566
DC Characteristics Except for PCI Interface
566
Power Circuit for PLL
567
Recommended Circuit for PLL
567
AC Characteristics
568
MASTERCLK AC Characteristics
568
Power on AC Characteristics
568
SDRAM Interface AC Characteristics
569
External Bus Interface AC Characteristics
570
PCI Interface AC Characteristics (33 Mhz)
571
DMA Interface AC Characteristics
572
Interrupt Interface AC Characteristics
574
SIO Interface AC Characteristics
574
PIO Interface AC Characteristics
574
AC-Link Interface AC Characteristics
576
NAND Flash Memory Interface AC Characteristics
577
CHI Interface AC Characteristics
578
SPI Interface AC Characteristics
579
Pin Layout, Package
581
Pin Layout
581
Package
586
Usage Notes
587
Limitation on DMA Data Chaining
587
Limitation on a Register Read after an SIO Software Reset
587
Other Precautions
587
Appendix A. TX49/H2 Core Supplement
589
Processor ID
589
Interrupts
589
Bus Snoop
589
Halt/Doze Mode
589
Memory Access Order
589
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