Interrupt Edge Detection Clear Register (Iredc) 0Xf660 - Toshiba TMPR4925 Manual

15.4.13 Interrupt Edge Detection Clear Register (IREDC)
31
15
Reserved
Bits Mnemonic Field Name
⎯
31:9 Reserved
Edge Detection
8 EDCE0
Clear Enable 0
⎯
7:4 Reserved
3:0 EDCS0 Edge Detection
Clear Source 0
25 24 23
Reserved
9 8 7
EDCE0
R/W1C
0
Edge Detection Clear Enable 0 (Initial value: 0, R/W1C)
Clears edge detection of interrupts specified by the EDCS0 field.
0: Does not clear.
1: Clears.
Value always becomes "0" when this bit is read.
Edge Detection Clear Source 0 (Initial value: 0x0, R/W1C)
These bits specify the interrupt source to be cleared.
1111: (Reserved)
1110: (Reserved)
1101: (Reserved)
1100: (Reserved)
1011: (Reserved)
1010: (Reserved)
1001: External INT[7] interrupt
1000: External INT[6] interrupt
0111: External INT[5] interrupt
0110: External INT[4] interrupt
0101: External INT[3] interrupt
0100: External INT[2] interrupt
0011: External INT[1] interrupt
0010: External INT[0] interrupt
0001: (Reserved)
0000: (Reserved)
Figure 15.4.13 Interrupt Status Control Register
15-23
Chapter 15 Interrupt Controller
0xF660
20 19
4 3
Reserved EDCS0
Explanation
⎯
⎯
16
: Type
: Initial value
0
R/W : Type
0000 : Initial value