P2G I/O Space Control Register (P2Gioctr) 0Xd19C - Toshiba TMPR4925 Manual

10.4.52 P2G I/O Space Control Register (P2GIOCTR)
31
15
AM[15:8]
R/W
0x00
Bits Mnemonic Field Name
⎯
31:16 Reserved
15:8 AM[15:8] Address Mask
⎯
7:2 Reserved
1 P2GIOEN I/O Space Enable Target I/O Space Enable (Initial value: 0, R/W) Controls whether the I/O Space for
0 BSWAP Byte Swap
Reserved
8 7
PCI-Bus to G-Bus Address Mask (Initial value: 0x00, R/W)
Sets the bits to be subject to address comparison. See 10.3.5 for more information.
When setting a I/O space size of 256 B (0x0000_0100) for example, the value
becomes 0x00.
target access is valid or invalid.
When this bit is set to invalid, Writes to the I/O Space Base Address Register of the
PCI Configuration Register become invalid. Also, "0" is returned to Reads as a
response.
1: Validates I/O Space for target access.
0: Invalidates I/O Space for target access.
Byte Swap Disable
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W) Sets the byte swapping
of the I/O Space for target access.
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "0" when in the
Big Endian Mode, the byte order of transfer to the I/O Space through DWORD (32-bit)
access will not change.
Figure 10.4.52 P2G I/O Space Control Register
10-81
Chapter 10 PCI Controller
0xD19C
2
Reserved
P2GIOEN
R/W
Description
⎯
⎯
16
: Type
: Initial value
1 0
BSWAP
R/W : Type
0 0/1 : Initial value