Toshiba TMPR4925 Manual page 135

Bits Mnemonic Field Name
11:8 CS Channel Size
7 BC Byte Control
6 RDY Ready Input
Mode
5:4 SP Bus Speed
3 ME Master Enable
2:0 SHWT Set Up/Hold Wait
Time
Figure 7.4.1 External Bus Channel Control Register (3/3)
Chapter 7 External Bus Controller
External Bus Control Channel Size (Initial value: 0010(ch0,7)/0000(ch1-6), R/W)
Specifies the channel memory size.
0000: 1 MB 0101: 32 MB
0001: 2 MB 0110: 64 MB
0010: 4 MB 0111: 128 MB
0011: 8 MB 1000: 256 MB
0100: 16 MB *1001: 512 MB
* The channel memory size can be set up to 512 MB when the memory bus width is
16 bits, or up to 256 MB when the memory bus width is 8 bits. No size larger than this
can be set.
External Bus Byte Control (Initial value: A[11](ch0,7)/0(ch1-6), R/W)
Specifies whether to use the BWE*[3:0] signal as an asserted Byte Write Enable
signal (BWE*[3:0]) only during a Write cycle, or to use it as an asserted Byte Enable
signal (BE*[3:0]) that is asserted during both Read and Write cycles.
0: Byte Enable (BE *[3:0])
1: Byte Write Enable (BWE*[3:0])
External Bus Control Ready Input Mode (Initial value: 0(ch0-6)/1(ch7), R/W)
Specifies whether to use the Ready mode.
0: Disable the Ready mode.
1: Enable the Ready mode.
Note: The Ready mode cannot be used when the Page mode is selected.
External Bus Control Bus Speed (Initial value: A[4:3]/00, R/W)
Specifies the External Bus speed.
00: 1/4 speed (1/4 of the GBUSCLK frequency)
01: 1/3 speed (1/3 of the GBUSCLK frequency)
10: 1/2 speed (1/2 of the GBUSCLK frequency)
11: Full speed (same frequency as GBUSCLK)
External Bus Control Master Enable (Initial value: A[8]/0, R/W)
Enables a channel.
0: Disable channel
1: Enable channel
Note: EBCCR0.ME bit is set when ADDR[8:6] equal to "1xx" as the default.
EBCCR7.ME bit is set when ADDR[8:6] equal to "010" as the default.
The default value for the ME bit of Channel 7 is "1" when Boot signal ADDR[8:6] is
010b. The value 010b cannot be used as Boot signal ADDR[8:6]. If the default value
of the ME bit for Channel 7 is "1", please confirm that Boot signal ADDR[8:6] is not
010b.
External Bus Control Setup/Hold Wait Time (Initial value: 000(ch0-6)/111(ch7), R/W)
Specifies the wait count when switching between the Address and Chip Enable
signal, or the Chip Enable Signal and Write Enable/Output Enable signal.
* 000: Disable 100: 4 wait cycles
001: 1wait cycle 101: 5 wait cycles
010: 2 wait cycles 110: 6 wait cycles
011: 3 wait cycles 111: 7 wait cycles
* Set this bit field to "0" when using it in the Page mode or when performing Burst
access.
7-27
Description
*1010: 1 GB
1011-1111: Reserved