Toshiba TX49 TMPR4937 Manual

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64-Bit TX System RISC

TX49 Family

TMPR4937

Rev. 2.0

Table of Contents

Summary of Contents for Toshiba TX49 TMPR4937

Page 1 64-Bit TX System RISC TX49 Family TMPR4937 Rev. 2.0...
Page 2 Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
Page 3 TMPR4937 64-bit RISC microprocessor. This databook is written so as to be accessible to engineers who may be designing a TOSHIBA microprocessor into their products for the first time. No prior knowledge of this device is assumed. What we offer here is basic information about the microprocessor, a discussion of the application fields in which the microprocessor is utilized, and an overview of design methods.
Page 5: Table Of Contents
Table of Contents Table of Contents Handling precautions TMPR4937 1. Overview and Features ............................1-1 Overview................................ 1-1 Features ................................1-1 1.2.1 Features of the TX49/H3 core......................1-2 1.2.2 Features of TX4937 peripheral functions .................... 1-2 2. Configuration................................2-1 TX4937 block diagram ..........................2-1 3.
Page 6 Table of Contents 6.2.2 Power Reduction for Peripheral Modules.................... 6-5 Power-On Sequence ............................6-6 7. External Bus Controller ............................7-1 Features ................................7-1 Block Diagram ............................... 7-2 Detailed Explanation............................7-3 7.3.1 External Bus Control Register ......................7-3 7.3.2 Global/Boot-up Options........................7-4 7.3.3 Address Mapping..........................
Page 7 Table of Contents 8.4.8 DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) ........8-37 8.4.9 DMA Count Register (DM0CNTRn, DM1CNTRn)................8-38 8.4.10 DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ............8-39 Timing Diagrams ............................8-40 8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM) ..........8-40 8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM) ..........
Page 8 Table of Contents 10.1.2 Initiator Function ..........................10-1 10.1.3 Target Function ..........................10-2 10.1.4 PCI Arbiter............................10-2 10.1.5 PDMAC (PCI DMA Controller)......................10-2 10.2 Block Diagram ............................. 10-3 10.3 Detailed Explanation............................ 10-4 10.3.1 Terminology Explanation ........................10-4 10.3.2 On-chip Register ..........................10-4 10.3.3 Supported PCI Bus Commands ......................
Page 9 Table of Contents 10.4.37 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0xD148......... 10-65 10.4.38 G2P I/O Space Address Mask Register (G2PIOMASK) 0xD14C ..........10-66 10.4.39 G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0xD150 ......10-67 10.4.40 G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0xD158 ......
Page 10 Table of Contents 11.4.5 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1) .................11-20 11.4.6 Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0xF414 (Ch. 1) ...............11-21 11.4.7 Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch.
Page 11 Table of Contents 14.3.7 GPIO Operation ..........................14-14 14.3.8 Interrupt ............................14-15 14.3.9 AC-link Low-power Mode ......................14-15 14.4 Registers..............................14-16 14.4.1 ACLC Control Enable Register 0xF700 ..................14-17 14.4.2 ACLC Control Disable Register 0xF704 ..................14-20 14.4.3 ACLC CODEC Register Access Register 0xF708 ................14-22 14.4.4 ACLC Interrupt Status Register 0xF710..................
Page 12 Table of Contents 16. Removed ................................16-1 17. Removed ................................17-1 18. Removed ................................18-1 19. Removed ................................19-1 20. Extended EJTAG Interface ........................... 20-1 20.1 Extended EJTAG Interface .......................... 20-1 20.2 JTAG Boundary Scan Test .......................... 20-2 20.2.1 JTAG Controller and Register ......................20-2 20.2.2 Instruction Register..........................
Page 13 Table of Contents TMPR4937 Revision History............................1...
Page 14 Table of Contents...
Page 15 Handling Precautions...
Page 17 It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property.
Page 18 1 Using Toshiba Semiconductors Safely...
Page 19 2 Safety Precautions 2. Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions.
Page 20 2 Safety Precautions General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation.
Page 21 2 Safety Precautions Precautions Specific to Each Product Group 2.2.1 Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1.
Page 22 2 Safety Precautions Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury.
Page 23 3 General Safety Precautions and Usage Considerations 3. General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. From Incoming to Shipping 3.1.1 Electrostatic discharge (ESD)
Page 24 3 General Safety Precautions and Usage Considerations (e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices. (g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions.
Page 25 3 General Safety Precautions and Usage Considerations • When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another.
Page 26 3 General Safety Precautions and Usage Considerations Storage 3.2.1 General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. Temperature: • Humidity: The storage area temperature should be kept within a temperature range of 5°C to 35°C, and relative humidity should be maintained at between...
Page 27 3 General Safety Precautions and Usage Considerations • If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture.
Page 28 This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e.g.
Page 29 3 General Safety Precautions and Usage Considerations CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow.
Page 30 For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor.
Page 31 3 General Safety Precautions and Usage Considerations 3.3.10 Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 Ω...
Page 32 3 General Safety Precautions and Usage Considerations 3.3.13 Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be taken into account.
Page 33 3 General Safety Precautions and Usage Considerations 3.4.2 Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user.
Page 34 3 General Safety Precautions and Usage Considerations (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For the minimum clearance specification between a device and a printed circuit board, refer to the relevant device’s datasheet and databook.
Page 35 3 General Safety Precautions and Usage Considerations 3.5.3 Soldering temperature profile The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used. (1) Using medium infrared ray reflow •...
Page 36 Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand.
Page 37 (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted).
Page 38 3 General Safety Precautions and Usage Considerations 3.5.10 Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 Repeated device mounting and usage Do not remount or re-use devices which fall into the categories listed below;...
Page 39 3 General Safety Precautions and Usage Considerations 3.6.5 Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current.
Page 40 3 General Safety Precautions and Usage Considerations 3-18...
Page 41 Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application.
Page 42 4 Precautions and Usage Considerations...
Page 43: Tmpr4937
TMPR4937 2005-3 Rev. 2.0...
Page 45 Conventions in this Manual Conventions in this Manual Value Conventions • Hexadecimal values are expressed as in the following example. (This value is expressed as 42 in the decimal system.) • KB (kilobyte) = 1,024 Bytes, MB (megabyte) = 1,024 × 1,024 = 1,048,576 Bytes, GB (gigabyte) = 1,024 ×...
Page 46 Any function described as a “diagnostic function” is used to facilitate operation evaluations. The operation of such functions is not guaranteed. References 64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture (http://www.semicon.toshiba.co.jp/eng/index.html) MIPS RISC Architecture, Gerry Kane and Joe Heinrich (ISBN 0-13-590472-2) See MIPS Run, Dominic Sweetman (ISBN 1-55860-410-3) MIPS Publications (http://www.mips.com/publications/) PCI Local Bus Specification Revision 2.2 (http://www.pcisig.com/)
Page 47: Overview And Features
The TMPR4937 (TX4937) is a standard microcontroller that belongs to the 64-bit TX System RISC TX49 family. The TX4937 uses the TX49/H3 core as its CPU. The TX49/H3 core is a 64-bit RISC core that Toshiba developed based on the MIPS III architecture of MIPS Technologies, Inc. (MIPS). For details of the TX49/H3 core such as instruction sets, see “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core...
Page 48: Features Of The Tx49/H3 Core
Chapter 1 Overview and Features 1.2.1 Features of the TX49/H3 core The TX49/H3 core is a high-performance, low power consumption 64-bit RISC CPU core that Toshiba developed. • 64-bit operation • 32 64-bit integer general-purpose registers • 64 GB physical address space •...
Page 49 Chapter 1 Overview and Features (2) Direct Memory Access Controllers (DMAC) The TX4937 has two DMA Controllers for invoking DMA transfer with memory and I/O devices. Each DMA Controller has 4 built-in DMA Channels. • Can set internal/external DMA requests •...
Page 50 Chapter 1 Overview and Features (5) Serial I/O port (SIO) The TX4937 has an on-chip 2-channel asynchronous serial I/O interface (full duplex UART) • Full duplex UART × 2 channels • On-chip baud rate generator • FIFO Transmission: on-chip 8-bit × 8-stage FIFO Reception: on-chip 13-bit ×...
Page 51 Chapter 1 Overview and Features • Can select either the Edge or Level interrupt detection mode for each external interrupt • Has a built-in 16-bit read/write register as a flag register for interrupt requests. Can request interrupts to an external device or to the TX49/H3 core (IRC interrupt) (10) Extended EJTAGInterface The TX4937's Extended EJTAG (Extended Enhanced Joint Test Action Group) interface provides two functions: IEEE1149.1-compliant JTAG boundary scan testing and real-time...
Page 52 Chapter 1 Overview and Features...
Page 53: Configuration
Chapter 2 Configuration Configuration TX4937 block diagram Figure 2.1.1 is an internal block diagram of the TX4937. TX49/H3 Core I-Cache CPU core D-Cache TRST* DCLK PCST[8:0] TPC[3:1] G-Bus I/F HALTDOZE RESET* TEST[4:0]* CB[7:0] TEST SDCLK[3:0] BYPASSPLL* SDCLKIN CGRESET* RAS* MASTERCLK CAS* SDRAMC DQM[7:0]...
Page 54 Chapter 2 Configuration The TX4937 has the following blocks. (1) TX49/H3 Core: Consists of a CPU, System Control Coprocessor (CP0), Instruction cache, Data cache, Floating-point Unit (FPU), write buffer (WBU), Debugging Support Unit (DSU), and a G-Bus I/F. • FPU: An IEEE754-compliant single-precision or double-precision floating-point unit.
Page 55: Signals
Chapter 3 Signals Signals Pin Signal Description In the following tables, asterisks at the end of signal names indicate active-low signals. In the Type column, PU indicates that the pin is equipped with an internal pull-up resister and PD indicates that the pin is equipped with an internal pull-down resister.
Page 56: Sdram Interface Signals
Chapter 3 Signals 3.1.2 SDRAM Interface Signals Table 3.1.2 SDRAM Interface Signals Signal Name Type Description Initial State SDCLK[3:0] Output SDRAM Controller Clock All High Clock signals used by SDRAM. The clock frequency is the same as the G-Bus clock (GBUSCLK) frequency.
Page 57: External Interface Signals
Chapter 3 Signals 3.1.3 External Interface Signals Table 3.1.3 External Interface Signals Signal Name Type Description Initial State SYSCLK Output System Clock High Clock for external I/O devices. Outputs a clock in full speed mode (at the same frequency as the G-Bus clock (GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency), third speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at one quarter the GBUSCLK frequency).
Page 58: Dma Interface Signals
Chapter 3 Signals 3.1.4 DMA Interface Signals Table 3.1.4 DMA Interface Signals Signal Name Type Description Initial State DMAREQ[3:0] Input DMA Request Input (other than DMA transfer request signals from an external I/O device. DMAREQ[2]) The DMAREQ[2] signal shares the pin with the ACRESET* signal. The boot configuration signal on the ADDR[9] pin selects between DMAREQ[2] and ACRESET* (refer to Section “3.3 Pin multiplex”).
Page 59 Chapter 3 Signals Table 3.1.5 PCI Interface Signals (2/2) Signal Name Type Description Initial State DEVSEL* Input/output Device Select Input The target asserts this signal in response to access from the initiator. REQ[3:2]* Input Request Input Signals used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used.
Page 60: Serial I/O Interface Signals
Chapter 3 Signals 3.1.6 Serial I/O Interface Signals Table 3.1.6 Serial I/O Interface Signals Signal Name Type Description Initial State CTS [1:0]* Input SIO Clear to Send Input CTS* signals. RTS [1:0]* Output SIO Request to Send All Low RTS* signals. RXD[1:0] Input SIO Receive Data...
Page 61: Ac-Link Interface Signals
Serial, Time Division Multiplexed, AC ‘97 Input Stream Input When this pin is used as SDIN[1], pull down by the resister on the board. (Regarding the value of register, please ask the Engineering Department in Toshiba). SDIN[0] Input Serial, Time Division Multiplexed, AC '97 Input Stream Input SDIN[0] shares the pin with the PIO[3] signal.
Page 62: Extended Ejtag Interface Signals
Chapter 3 Signals 3.1.11 Extended EJTAG Interface Signals Table 3.1.11 Extended EJTAG Interface Signals Signal Name Type Description Initial State Input JTAG Test Clock Input Input Clock input signal for JTAG. TCK is used to execute JTAG instructions and input/output data. TDI/DINT* Input JTAG Test Data Input/Debug Interrupt...
Page 63: Initialization Signal
Test pins. These pins must be left open or fixed to High. TEST[1]* may be used when debugging the system. Toshiba recommends that your board design enable the pin to be driven low after the TX4937 is mounted on the PC board.
Page 64: Boot Configuration
Chapter 3 Signals Boot Configuration The ADDR[19:0] and DATA[15:0] signals can also function as configuration signals for initially setting various functions upon booting the system. The states of the configuration signals immediately after the RESET* or CGRESET* signal is deasserted are read as initial values for the TX4937 internal registers. A High signal level sets a value of 1 and a Low signal level sets a value of 0.
Page 65 Chapter 3 Signals Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (1/2) Corresponding Configuration Signal Description Register Bit Determined at ADDR[19] PCI Controller Mode Select CCFG. PCIMODE RESET* deassert edge Specifies the operating mode of the TX4937 PCI controller. L = Satellite H = Host ADDR[18]...
Page 66 Chapter 3 Signals Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (2/2) Signal Corresponding Configuration Description Register Bit Determined at ADDR[4] Initial Setting of Boot PCFG[56:54] RESET* deassert edge Select initial setting derivability of SDRAM interface signals L = 8mA H = 16mA DATA[63:0], CB[7:0], DQM[7:0] ADDR[3:0]...
Page 67 Chapter 3 Signals Table 3.2.3 Boot Configuration Specified with the DATA[22:0] Signals Corresponding Configuration Signal Description Register Bit Determined at ⎯ ⎯ DATA[22:16] Reserved DATA[15:8] Boot Configuration CCFG.BCFG RESET* deassert edge Reads the board information and accordingly sets the boot configuration field (BCFG) of the chip configuration register (CCFG).
Page 68: Pin Multiplex
Chapter 3 Signals Pin multiplex The TX4937 has some multiplexed pins. Each pin is used for different functions depending on the settings of the ADDR[18]/[9] boot configuration signal. Table 3.3.1 shows how to set the function for each pin. Table 3.3.1 Pin multiplex Function on pin-multiplex Signal PIO[15:8]...
Page 69: Address Mapping
Chapter 4 Address Mapping Address Mapping This chapter explains the physical address map of TX4937. Please refer to "64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture" about the details of mapping to a physical address from the virtual address of TX49/H3 core. TX4937 Physical Address Map TX4937 supports up to 64G (2 ) bytes of physical address.
Page 70: Register Map
Chapter 4 Address Mapping Register Map 4.2.1 Addressing TX4937 internal registers are to be accessed through 64 K bytes address space that is based on physical address 0xF_FF1F_0000 or pointed address by RAMP register (refer to 5.2.7). Figure 4.2.1 shows how to generate internal register address. Physical address 1 and physical address 2 shown Figure 4.2.1 access the same register.
Page 71 Chapter 4 Address Mapping 4.2.3 Register Map Please refer to “10.5 PCI Configuration Space Register” about PCI configuration register. Table 4.2.2 Register Map Offset Address Peripheral Controller Detail ⎯ 0x0000 to 0x7FFF Reserved 0x8000 to 0x8FFF SDRAMC Refer to “9.4” 0x9000 to 0x9FFF EBUSC Refer to “7.4”...
Page 72 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (1/9) Offset Address Register Size (bit) Register Symbol Register Name SDRAM Controller (SDRAMC) 0x8000 SDCCR0 SDRAM Channel Control Register 0 0x8008 SDCCR1 SDRAM Channel Control Register 1 0x8010 SDCCR2 SDRAM Channel Control Register 2 0x8018 SDCCR3 SDRAM Channel Control Register 3...
Page 73 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (2/9) Offset Address Register Size (bit) Register Symbol Register Name DMA Controller (DMAC0) 0xB000 DM0CHAR0 DMAC0 Chain Address Register 0 0xB008 DM0SAR0 DMAC0 Source Address Register 0 0xB010 DM0DAR0 DMAC0 Destination Address Register 0 0xB018 DM0CNTR0 DMAC0 Count Register 0...
Page 74 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (3/9) Offset Address Register Size (bit) Register Symbol Register Name DMA Controller (DMAC1) 0xB800 DM1CHAR0 DMAC1 Chain Address Register 0 0xB808 DM1SAR0 DMAC1 Source Address Register 0 0xB810 DM1DAR0 DMAC1 Destination Address Register 0 0xB818 DM1CNTR0 DMAC1 Count Register 0...
Page 75 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (4/9) Offset Address Register Size (bit) Register Symbol Register Name PCI Controller (PCIC) 0xD000 PCIID ID Register (Device ID, Vendor ID) 0xD004 PCISTATUS PCI Status, Command Register (Status, Command) 0xD008 PCICCREV Class Code, Revision ID Register (Class Code, Revision ID) PCI Configuration 1 Register 0xD00C PCICFG1...
Page 76 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (5/9) Offset Address Register Size (bit) Register Symbol Register Name 0xD120 G2PM0GBASE G2P Memory Space 0 G-Bus Base Address Register 0xD128 G2PM1GBASE G2P Memory Space 1 G-Bus Base Address Register 0xD130 G2PM2GBASE G2P Memory Space 2 G-Bus Base Address Register 0xD138 G2PIOGBASE...
Page 77 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (6/9) Offset Address Register Size (bit) Register Symbol Register Name Configuration 0xE000 CCFG Chip Configuration Register 0xE008 REVID Chip Revision ID Register 0xE010 PCFG Pin Configuration Register 0xE018 TOEA Timeout Error Access Address Register 0xE020 CLKCTR Clock Control Register...
Page 78 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (7/9) Offset Address Register Size (bit) Register Symbol Register Name Serial I/O (Channel 0) 0xF300 SILCR0 Line Control Register 0 0xF304 SIDICR0 DMA/Interrupt Control Register 0 0xF308 SIDISR0 DMA/ Interrupt Status Register 0 0xF30C SISCISR0 Status Change Interrupt Status Register 0...
Page 79 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (8/9) Offset Address Register Size (bit) Register Symbol Register Name Interrupt Controller (IRC) 0xF510 IRFLAG0 Interrupt Request Flag 0 Register 0xF514 IRFLAG1 Interrupt Request Flag 1 Register 0xF518 IRPOL Interrupt Request Polarity Control Register 0xF51C IRRCNT Interrupt Request Control Register...
Page 80 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (9/9) Offset Address Register Size (bit) Register Symbol Register Name AC-link Controller (ACLC) 0xF700 ACCTLEN ACLC Control Enable Register 0xF704 ACCTLDIS ACLC Control Disable Register 0xF708 ACREGACC ACLC CODEC Register Access Register 0xF710 ACINTSTS ACLC Interrupt Status Register...
Page 81: Configuration Registers
Chapter 5 Configuration Registers Configuration Registers Detailed Description The configuration registers set up and control the basic functionality of the entire TX4937. Refer to Section 5.2 for details of each configuration register. Also refer to sections mentioned in the description about each bit field.
Page 82: Registers
Chapter 5 Configuration Registers Registers Table 5.2.1 lists the configuration registers. Table 5.2.1 Configuration Register Mapping Offset Address Size in Bits Register Symbol Register Name 0xE000 CCFG Chip Configuration Register 0xE008 REVID Chip Revision ID Register 0xE010 PCFG Pin Configuration Register 0xE018 TOEA Timeout Error Access Address Register...
Page 83: Chip Configuration Register (Ccfg) 0Xe000
Chapter 5 Configuration Registers 5.2.1 Chip Configuration Register (CCFG) 0xE000 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. Reserved : Type : Initial value Reserved BCFG...
Page 84 Chapter 5 Configuration Registers Mnemonic Field Name Description Initial Value Read/Write PCI 66MHz Used to inform the device connected to the PCI bus that a 66 PCI66 Mode MHz operation is to be performed. This bit is valid only when the PCI controller of the TX4937 is in host mode.
Page 85 Chapter 5 Configuration Registers Mnemonic Field Name Description Initial Value Read/Write 12:10 PCIDIVMODE PCICLK Specifies the frequency division ratio of the PCI bus clock ADDR[11:10] Frequency output (PCICLK[5:0]) frequency to the clock frequency Division Ratio (CPUCLK) of the TX49/H3 core. 001: PCICLK frequency = CPUCLK frequency ÷...
Page 86: Chip Revision Id Register (Revid) 0Xe008
Indicates the minor extra code. Code MJREV Major Revision Indicates the major revision of the product. Code Contact Toshiba technical staff for the latest information. MINREV Minor Revision Indicates the minor revision of the product. Code Contact Toshiba technical staff for the latest information.
Page 87: Pin Configuration Register (Pcfg) 0Xe010
Chapter 5 Configuration Registers 5.2.3 Pin Configuration Register (PCFG) 0xE010 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. Reserved DRVCB DRVDQM DRVCKE DRVRAS DRVCAS DRVWE DRVDATA DRVADDR...
Page 88 Chapter 5 Configuration Registers Mnemonic Field Name Description Initial Value Read/Write WE Signal DRVWE Specifies the driving capability of the WE* signal. ADDR[5] Control L : 0 = 8 mA H : 1 = 16 mA SDRAM CS Specifies the driving capability of the SDCS[3:0]* signals. ADDR[5] 48:45 DRVCS[3:0]...
Page 89 Chapter 5 Configuration Registers Mnemonic Field Name Description Initial Value Read/Write Shared-Pin Indicates which function, PIO[15:8] or CB[7:0], the shared pins SEL1 ADDR[18] Status 1 are set to. L: 0 = The shared pins are set to PIO[15:8]. H: 1 = The shared pins are set to CB[7:0]. ⎯...
Page 90: Timeout Error Access Address Register (Toea) 0Xe018
Chapter 5 Configuration Registers 5.2.4 Timeout Error Access Address Register (TOEA) 0xE018 Reserved : Type : Initial value Reserved TOEA[35:32] : Type : Initial value TOEA[31:16] : Type : Initial value TOEA[15:0] : Type : Initial value Mnemonic Field Name Description Initial Value Read/Write ⎯...
Page 91: Clock Control Register (Clkctr) 0Xe020
Chapter 5 Configuration Registers 5.2.5 Clock Control Register (CLKCTR) 0xE020 Bit 32 and bits 15-0 are reset bits for the on-chip peripheral modules. To bring on-chip peripheral modules out of the reset state, the corresponding bits must be cleared by software. Before clearing them, wait at least 128 CPU clock cycles after they are set.
Page 92 Chapter 5 Configuration Registers Mnemonic Field Name Description Initial Value Read/Write SIO0 Clock SIO0CKD Controls clock pulses for the SIO0 controller. Disable 0 = Supply clock pulses. 1 = Do not supply clock pulses. SIO1 Clock SIO1CKD Controls clock pulses for the SIO1 controller. Disable 0 = Supply clock pulses.
Page 93: G-Bus Arbiter Control Register (Garbc) 0Xe030
Chapter 5 Configuration Registers 5.2.6 G-Bus Arbiter Control Register (GARBC) 0xE030 Reserved : Type : Initial value Reserved : Type : Initial value Reserved ARBMD : Type : Initial value PRIORITY Reserved : Type 000_001_010_011_100 : Initial value Mnemonic Field Name Description Initial Value Read/Write ⎯...
Page 94 Chapter 5 Configuration Registers 5.2.7 Register Address Mapping Register (RAMP) 0xE048 Reserved : Type : Initial value Reserved : Type : Initial value Reserved RAMP[35:32] : Type : Initial value RAMP[31:16] : Type 0xFF1F : Initial value Mnemonic Field Name Description Initial Value Read/Write ⎯...
Page 95: Clocks
Chapter 6 Clocks Clocks TX4937 Clock Signals Figure 6.1.1 shows the configuration of TX4937 blocks and clock signals. Table 6.1.1 describes each clock signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is 266 MHz. Table 6.1.3 shows the relationship among different clock signals when the CPU clock frequency is 300 MHz.
Page 96 Chapter 6 Clocks Table 6.1.1 TX4937 Clock Signals (1/2) Related Related Registers Configuration Signals (Refer to Chapters 5 Clock Input/Output Description (Refer to Section and 10.) 3.2.) ⎯ ⎯ MASTERCLK Input Master input clock for the TX4937. The TX4937 internal clock generator multiplies or divides MASTERCLK to generate internal clock pulses.
Page 97 Chapter 6 Clocks Table 6.1.1 TX4937 Clock Signals (2/2) Related Related Registers Configuration Signals Clock Input/Output Description (Refer to Chapters 5 (Refer to Section and 10.) 3.2.) PCICLK[5:0] Output Clock supplied to devices on the PCI bus. ADDR[11:10] CCFG.PCIDIVMODE PCFG.PCICLKEN[5:0] The PCICLKEN bit of the PCFG register can disable the output of PCICLK.
Page 98 Chapter 6 Clocks Table 6.1.2 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 266 MHz) Master Clock (Input) Internal Clock External Clock (Output) and Boot Configured Settings SYSCLK (MHz) PCICLK[5:0] (MHz) † Boot CCFG Settings SDCLK Boot Configured Settings Configured MASTERCLK CPUCLK...
Page 99: Power-Down Mode
Chapter 6 Clocks Table 6.1.4 Relationship Among Different Clock Frequencies (for TMPR4937XBG-333, CPUCLK = 333 MHz) Master Clock (Input) Internal Clock External Clock (Output) and Boot Configured Settings SYSCLK (MHz) PCICLK[5:0] (MHz) † Boot CCFG Settings SDCLK Configured Boot Configured Settings MASTERCLK CPUCLK GBUSCLK...
Page 100: Power-On Sequence
Chapter 6 Clocks Power-On Sequence MASTERCLK RESET* CGRESET* PLL settling time PLL1 output CPUCLK GBUSCLK PCICLK PCICLKIN (when PCICLK is fed back) PLL settling time PLL2 output PCICLKO (clock for TX4937 PCI controller) Figure 6.3.1 Power-On Sequence...
Page 101: External Bus Controller
Chapter 7 External Bus Controller External Bus Controller Features The External Bus Controller is used for accessing ROM, SRAM memory, and I/O peripherals. The features of this bus are described below. (1) 8 independent channels (2) Supports access to ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, flash memory, and I/O peripherals.
Page 102: Block Diagram
Chapter 7 External Bus Controller Block Diagram External Bus Controller (EBUSC) G-Bus Channel Control G-Bus I/F Register CE*[7:0] ACEHOLD Register Address Address Decoder Decoder Timing Boot SWE* Control Options BWE*[3:0]/BE*[3:0] Host I/F Timing Control ACK*/READY ACE* Channel Control Register IOR* IOW* Address CS[1:0]*...
Page 103: Detailed Explanation
Chapter 7 External Bus Controller Detailed Explanation 7.3.1 External Bus Control Register The External Bus Controller (EBUSC) has eight channels. This register contains one Channel Control Register (EBCCRn) for each channel, and all settings can be made independently for each channel. Either Word or Double-word access is possible for a Control Register.
Page 104: Global/Boot-Up Options
Chapter 7 External Bus Controller 7.3.2 Global/Boot-up Options In addition to the settings made separately for each channel, the Channel Control Registers can also use global options that make settings common to all channels. External Bus Controller Channel 0 can be used as a Boot memory channel. Channel 0 is set by the external pins (Boot pins) during reset.
Page 105: Address Mapping
Chapter 7 External Bus Controller 7.3.3 Address Mapping Each of the eight channels can use the Base Address field (EBCCRn.BA[35:20]) and the Channel Size field (EBCCRn.CS[3:0]) of the External Bus Channel Control Register to map to any physical address. A channel is selected when the following equation becomes True. paddr[35:20] &...
Page 106: External Address Output
Chapter 7 External Bus Controller 7.3.4 External Address Output The maximum memory space size for each channel is 1 GB (230B). Addresses are output by dividing the 20-bit ADDR[19:0] signal into two parts: the upper address and the lower address. The address bit output to each bit of the ADDR[19:0] signal changes according to the setting of the channel data bus width.
Page 107: Data Bus Size
Chapter 7 External Bus Controller 7.3.5 Data Bus Size The External Bus Controller supports devices with a data bus width of 8 bits, 16 bits, and 32 bits. The data bus width is selected using the BSZ field of the Channel Control Register (EBCCRn). The address bits output to each bit of the ADDR[19:0] signal change according to the mode.
Page 108 Chapter 7 External Bus Controller 7.3.5.3 8-bit Bus Width Mode DATA[7:0] becomes valid. Bits [19:0] of the physical address are output to ADDR[19:0]. The internal address bits [27:20], which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the address is shifted up two bits or more relative to the 32-bit bus mode when output.
Page 109: Access Mode
Chapter 7 External Bus Controller 7.3.6 Access Mode The following four modes are available as controller access modes. These modes can be set separately for each channel. • Normal mode • Page mode • External ACK mode • Ready mode Depending on the combination of modes in each channel, either of two modes in which the ACK*/Ready signal operates differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is selected by the ACK*/Ready Mode bit (CCFG.ARMODE) of the Chip Configuration Register.
Page 110 Chapter 7 External Bus Controller 7.3.6.1 Normal Mode When in this mode, the ACK*/Ready signal becomes an ACK* output when it is in the ACK*/Ready Dynamic mode. The ACK*/Ready signal becomes High-Z when it is in the ACK*/Ready Static mode. Wait cycles are inserted according to the EBCCRn.PWT and EBCCRn.WT value at the access cycle.
Page 111 Chapter 7 External Bus Controller 7.3.6.3 Ready Mode When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by Ready input from an external device. Ready input is internally synchronized. See Section “7.3.7.5 Ready Input Timing” for more information regarding the operation timing. When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is performed to see whether the Ready signal was asserted.
Page 112 Chapter 7 External Bus Controller 7.3.6.4 Page Mode When in this mode, the ACK*/Ready pin becomes ACK* output when it is in the Dynamic mode. When it is in the ACK*/Ready Static mode, the ACK*/Ready signal becomes HiZ. Wait cycles are inserted into the access cycle according to the values of EBCCRn.PWT and EBCCRn.WT.
Page 113: Access Timing
Chapter 7 External Bus Controller 7.3.7 Access Timing 7.3.7.1 SHWT Option The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel Control Register is a value other than “0.” This option inserts Setup cycles and Hold cycles between signals as follows.
Page 114 Chapter 7 External Bus Controller SYSCLK CE*/BE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Output) EBCCRn.PWT:WT=0 EBCCRn.SHWT=1 Figure 7.3.6 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle) 7.3.7.2 ACK*/READY Input/Output Switching Timing When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When in the ACK*/Ready Dynamic mode, the ACK*/Ready signal is an input signal when in the External ACK mode or the Ready mode, but is an output signal in all other modes.
Page 115 Chapter 7 External Bus Controller 7.3.7.3 ACK* Output Timing (Normal Mode, Page Mode) When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK* signal becomes an output signal and is asserted for one clock cycle to send notification to the external device of the data Read and data Write timing.
Page 116 Chapter 7 External Bus Controller 7.3.7.4 ACK* Input Timing (External ACK Mode) The ACK* signal becomes an input signal when in the external ACK mode. During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is acknowledged (Figure 7.3.9 ACK* Input Timing (Single Read Cycle)).
Page 117 Chapter 7 External Bus Controller SYSCLK ADDR [19:0] DATA [31:0] ACK*/READY (Input) 2 clocks 2 clocks Latch Latch Acknowledge Acknowledge Data Data ACK* ACK* EBCCRn.SHWT=0 Figure 7.3.11 ACK* Input Timing (Burst Read Cycle) SYSCLK ADDR [19:0] 3 clocks 3 clocks SWE*/BWE* 4 clocks 4 clocks...
Page 118 Chapter 7 External Bus Controller 7.3.7.5 Ready Input Timing The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input timing is the same as the ACK* input timing explained in 7.3.7.4 ACK* Input Timing (External ACK Mode) with the two following exceptions.
Page 119: Clock Options
Chapter 7 External Bus Controller SYSCLK ADDR [19:0] 3 clocks SWE*/BWE* DATA [31:0] ACK*/READY 4 clocks (Input) Acknowledge Ready EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 SYSCLK ADDR [19:0] 3 clocks SWE*/BWE* DATA [31:0] 4 clocks ACK*/READY (Input) Start Ready Acknowledge Ready Check EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Figure 7.3.14 Ready Input Timing (Write Cycle) 7.3.8 Clock Options...
Page 120: Register
Chapter 7 External Bus Controller Register Table 7.4.1 External Bus Controller (EBUSC) Registers Offset Address Bit Width Register Symbol Register Name 0x9000 EBCCR0 E-Bus Channel Control Register 0 0x9008 EBCCR1 E-Bus Channel Control Register 1 0x9010 EBCCR2 E-Bus Channel Control Register 2 0x9018 EBCCR3 E-Bus Channel Control Register 3...
Page 121: 0X9010 (Ch. 2), 0X9018 (Ch. 3) 0X9020 (Ch. 4), 0X9028 (Ch. 5) 0X9030 (Ch. 6), 0X9038 (Ch. 7)
Chapter 7 External Bus Controller 7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7) Channel 0 can be used as Boot memory. Therefore, the default is set by the Boot signal (see 7.3.2 Global/Boot-up Options).
Page 122 Chapter 7 External Bus Controller Mnemonic Field Name Description Read/Write Page Mode 17:16 External Bus Control Page Mode Wait Time (Default: 11 / 00) Wait time Specifies the wait cycle count during Burst access when in the Page mode. 00: 0 wait cycles 10: 2 wait cycles 01: 1 wait cycle 11: 3 wait cycles...
Page 123 Chapter 7 External Bus Controller Mnemonic Field Name Description Read/Write Ready Input External Bus Control Ready Input Mode (Default: 0) Mode Specifies whether to use the Ready mode. 0: Disable the Ready mode. 1: Enable the Ready mode. Note: The Ready mode cannot be used when the Page mode is selected. Bus Speed External Bus Control Bus Speed (Default: ADDR[7:6] / 00) Specifies the External Bus speed.
Page 124: Timing Diagrams
Chapter 7 External Bus Controller Timing Diagrams Please take the following points into account when referring to the timing diagrams. (1) The clock frequency of the SYSCLK signal can be set to one of the following divisions of the internal bus clock (GBUSCLK): 1/1, 1/2, 1/3, or 1/4.
Page 125: Ace* Signal
Chapter 7 External Bus Controller 7.5.1 ACE* Signal Figure 7.5.1 ACE* Signal (CCFG.ACEHOLD=1, PWT: WT=0, SHWT=0, Normal) 7-25...
Page 126 Chapter 7 External Bus Controller Figure 7.5.2 ACE* Signal (CCFG.ACEHOLD=0, PWT: WT=0, SHWT=0, Normal) 7-26...
Page 127: Normal Mode Access (Single, 32-Bit Bus)
Chapter 7 External Bus Controller 7.5.2 Normal mode access (Single, 32-bit Bus) Figure 7.5.3 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-27...
Page 128 Chapter 7 External Bus Controller SYSCLK ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA[31:0] ACK* Figure 7.5.4 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-28...
Page 129 Chapter 7 External Bus Controller Figure 7.5.5 1-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-29...
Page 130 Chapter 7 External Bus Controller Figure 7.5.6 1-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-30...
Page 131: Normal Mode Access (Burst, 32-Bit Bus)
Chapter 7 External Bus Controller 7.5.3 Normal mode access (Burst, 32-bit Bus) Figure 7.5.7 4-word Burst Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-31...
Page 132 Chapter 7 External Bus Controller SYSCLK ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA[31:0] ACK* Figure 7.5.8 4-word Burst Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-32...
Page 133: Normal Mode Access (Single, 16-Bit Bus)
Chapter 7 External Bus Controller 7.5.4 Normal Mode Access (Single, 16-bit bus) Figure 7.5.9 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-33...
Page 134 Chapter 7 External Bus Controller Figure 7.5.10 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-34...
Page 135 Chapter 7 External Bus Controller Figure 7.5.11 Half-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-35...
Page 136 Chapter 7 External Bus Controller Figure 7.5.12 Half-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-36...
Page 137: Normal Mode Access (Burst, 16-Bit Bus)
Chapter 7 External Bus Controller 7.5.5 Normal Mode Access (Burst, 16-bit Bus) Figure 7.5.13 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-37...
Page 138 Chapter 7 External Bus Controller Figure 7.5.14 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-38...
Page 139: Normal Mode Access (Single, 8-Bit Bus)
Chapter 7 External Bus Controller 7.5.6 Normal Mode Access (Single, 8-bit Bus) Figure 7.5.15 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-39...
Page 140 Chapter 7 External Bus Controller Figure 7.5.16 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-40...
Page 141 Chapter 7 External Bus Controller SYSCLK ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [7:0] ACK* Figure 7.5.17 1-byte Single Write (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) SYSCLK ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [7:0] ACK* Figure 7.5.18 1-byte Single Read (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) 7-41...
Page 142: Normal Mode Access (Burst, 8-Bit Bus)
Chapter 7 External Bus Controller 7.5.7 Normal Mode Access (Burst, 8-bit Bus) Figure 7.5.19 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-42...
Page 143 Chapter 7 External Bus Controller Figure 7.5.20 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-43...
Page 144: Page Mode Access (Burst, 32-Bit Bus)
Chapter 7 External Bus Controller 7.5.8 Page Mode Access (Burst, 32-bit Bus) Figure 7.5.21 8-word Burst Write (WT=1, PWT=0, SHWT=0, 4-page, 32-bit Bus) 7-44...
Page 145 Chapter 7 External Bus Controller Figure 7.5.22 4-word Burst Read (WT=2, PWT=1, SHWT=0, 4-page, 32-bit Bus) 7-45...
Page 146: External Ack Mode Access (32-Bit Bus)
Chapter 7 External Bus Controller 7.5.9 External ACK Mode Access (32-bit Bus) SYSCLK ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA[31:0] ACK* Note 1: The TX4937 sets the ACK* signal to High Impedance in the S1 State. Note 2: External devices drive the ACK* signal to Low (assert the signal) by the ES1 State. Note 3: External devices drive the ACK* signal to High (deassert the signal) in the ES2 State.
Page 147 Chapter 7 External Bus Controller Figure 7.5.25 4-word Burst Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus) 7-47...
Page 148 Chapter 7 External Bus Controller Figure 7.5.26 4-word Burst Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus) 7-48...
Page 149 Chapter 7 External Bus Controller Figure 7.5.27 Double-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) 7-49...
Page 150 Chapter 7 External Bus Controller Figure 7.5.28 Double-word Single Read (0 Wait, SHWT=2, External ACK*, 32-bit Bus) 7-50...
Page 151 Chapter 7 External Bus Controller AS2 CS1 CS2 SW1 ES1 CH1 CH2 AH1 AH2 SYSCLK ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA[31:0] ACK* Figure 7.5.29 1-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) AS2 CS1 CH1 CH2 AH1 AH2 SYSCLK ADDR[19:0] ACE*...
Page 152: Ready Mode Access (32-Bit Bus)
Chapter 7 External Bus Controller 7.5.10 READY Mode Access (32-bit Bus) Figure 7.5.31 1-word Single Write (PWT: WT=2, SHWT=1, READY, 32-bit Bus) 7-52...
Page 153 Chapter 7 External Bus Controller Figure 7.5.32 1-word Single Read (PWT: WT=2, SHWT=1, READY, 32-bit Bus) 7-53...
Page 154: Flash Rom, Sram Usage Example
Chapter 7 External Bus Controller Flash ROM, SRAM Usage Example Figure 7.6.1 illustrates example Flash ROM connections, and Figure 7.6.2 illustrates example SRAM connections. Also, Figure 7.6.3 illustrates example connections with the SDRAM and the bus separated. Since connecting multiple memory devices such as SDRAM and ROM onto a single bus increases the load, 100 MHz class high-speed SDRAM access may not be performed normally.
Page 155 Chapter 7 External Bus Controller TX4937 SDRAM (x16 Bits) DQM[7] DQM[6] DQM[5] DQM[4] DQM[3] DQM[2] DQM[1] DQM[0] DQM[7:0] UDQM LDQM UDQM LDQM UDQM LDQM UDQM LDQM ADDR[17:5] ADDR[19:0] A[12:0] A[12:0] A[12:0] A[12:0] ADDR[19] ADDR[18] SDCS*[0] RAS* RAS* RAS* RAS* RAS* CAS* CAS* CAS*...
Page 156 Chapter 7 External Bus Controller 7-56...
Page 157: Dma Controller
Chapter 8 DMA Controller DMA Controller Features The TX4937 contains two four-channel DMA Controller (DMAC0, DMAC1) that executes DMA (Direct Memory Access) with memory and I/O devices. The DMA Controller has the following characteristics. <DMAC0, DMAC1> • Has four on-chip DMA channels •...
Page 158: Block Diagram
Chapter 8 DMA Controller Block Diagram DMAREQ[0] DMAC0 DM0CHAR0 DMA0 External DREQ0 Channel 0 DM0SAR0 Pins DMAACK[0] DM0DAR0 DACK0 DM0CNTR0 Internal I/O DM0SAIR0 Control 0 (Receive SIO ch1) DM0MCR DM0DAIR0 Block DM0CCR0 DM0MFDR PCFG.DMASEL0 DM0CSR0 G-Bus DMAREQ[1] DM0CHAR1 DMA0 External DREQ1 Channel 1 DM0SAR1...
Page 159 Chapter 8 DMA Controller DMAC0 DM1CHAR0 DMA1 DREQ0 Channel 0 DM1SAR0 Internal I/O DM1DAR0 (ACLC ch0) DACK0 DM1CNTR0 DM1SAIR0 Control 1 DM1MCR DM1DAIR0 Block DM1CCR0 DM1MFDR DM1CSR0 G-Bus DM1CHAR1 DMA1 DREQ1 Channel 1 DM1SAR1 Internal I/O DM1DAR1 (ACLC ch1) DMCK1 DM1CNTR1 DM1SAIR1 FIFO...
Page 160: Detailed Explanation
Chapter 8 DMA Controller Detailed Explanation 8.3.1 Transfer Mode The DMA Controller (DMAC0, DMAC1) supports five transfer mode types (refer to Table 8.3.1 below). The setting of the External Request bit (DMCCRn.EXTRQ) of the DMA Channel Control Register selects whether transfer with an I/O device is a DMA transfer. •...
Page 161: On-Chip Registers
Chapter 8 DMA Controller 8.3.2 On-chip Registers The DMA Controller has two shared registers that are shared by four channels. Section 8.4 explains each register in detail. • Shared Registers DMMCR: DMA Master Control Register DMMFDR: DMA Memory Fill Data Register •...
Page 162 Chapter 8 DMA Controller • When edge detection is set (DMCCRn.EGREQ = 1) Please set up assertion of the DMAREQ[n] signal so the DMAREQ[n] signal is asserted after the DMAACK[n] signal corresponding to a previously asserted DMAREQ[n] signal is deasserted. The DMAREQ[n] signal will not be detected even if it is asserted before DMAACK[n] is deasserted.
Page 163 Chapter 8 DMA Controller 8.3.3.2 Dual Address Transfer If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices and to external memory is each performed continuously. Each access is the same as normal access except when the DMAACK[n] signal is asserted. Please refer to “8.3.8 Dual Address Transfer”...
Page 164: Internal I/O Dma Transfer Mode
Chapter 8 DMA Controller When the Chain End bit (CHDN) is cleared, the DMADONE* signal is asserted when the DMAACK[n] signal for the last data transfer in a DMA transfer specified by the current DMA Channel Register is asserted. Namely, if the Link List Command chain is used, there is one assertion at the end of each data transfer specified by each Descriptor.
Page 165: Memory-Memory Copy Mode
Chapter 8 DMA Controller 8.3.5 Memory-Memory Copy Mode It is possible to copy memory from any particular address to any other particular address when in the Memory-Memory Copy mode. Set the DMA Channel Control Register (DMCCRn) as follows. • DMCCRn.EXTRQ = 0: Memory Transfer mode •...
Page 166 Chapter 8 DMA Controller 8.3.7.1 Channel Register Settings During Single Address Transfer Table 8.3.2 shows restrictions of the Channel Register settings during Single Address transfer. If these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit (CFERR) of the DMA Channel Status Register (DMCSRn) is set and DMA transfer is not performed.
Page 167 Chapter 8 DMA Controller 8.3.7.2 Burst Transfer During Single Address Transfer According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst transfer that spans across 32-double word boundaries. Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size (DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that were specified by a Burst transfer.
Page 168: Dual Address Transfer
Chapter 8 DMA Controller 8.3.8 Dual Address Transfer This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This applies to the following DMA transfer modes. • External I/O (Dual Address) transfer • Internal I/O DMA transfer •...
Page 169 Chapter 8 DMA Controller Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer DMSARn[2:0] DMDARn[2:0] Transfer Setting DMSAIRn DMDAIRn DMCCRn DMSAIRn DMDAIRn Size DMSAIRn DMDAIRn DMCNTRn setting is a setting is a REVBYTE setting is 0 setting is 0 (DMCCRn.XFSZ) negative negative...
Page 170 Chapter 8 DMA Controller Source Address FIFO (8 Double Words) Destination Address Figure 8.3.3 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 1) Figure 8.3.4 shows Dual Address Burst transfer when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is set to “0”, the lower 8 bits of the Transfer Start address for the transfer source are set to 0xA8, the lower 8 bits of the Transfer Start address for the transfer destination are set to (a) 0x28/(b) 0x30, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 double words.
Page 171 Chapter 8 DMA Controller When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to the Destination Address is divided into multiple 8-byte Single Write transfers, then transfer is executed. When the Burst Inhibit bit is set, the TX4937 always performs an 8-byte Single transfer. For accesses to an external I/O device, a Single transfer is divided into multiple accesses, depending on its bus width.
Page 172 Chapter 8 DMA Controller Source Address FIFO (8 Double Words) Destination Address (a) Address offset is equivalent (b) Address offset differs Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0) 8-16...
Page 173: Dma Transfer
Chapter 8 DMA Controller 8.3.9 DMA Transfer The sequence of DMA transfer that uses only the DMA Channel Register is as follows below. Select DMA request signal When performing external I/O or internal I/O DMA, set the DMA Request Select field (PCFG.DMASEL) of the Pin Configuration Register.
Page 174: Chain Dma Transfer
Chapter 8 DMA Controller 8.3.10 Chain DMA Transfer Table 8.3.4 shows the data structure in memory that the DMA Command Descriptor has. When the Simple Chain bit (SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial four double words are used.
Page 175 Chapter 8 DMA Controller “A” “D” “B” “E” “C” Figure 8.3.5 DMA Command Descriptor Chain The sequence of Chain DMA transfer is as follows below. Select DMA request signal When performing external I/O or internal I/O DMA, set the DMA Request Select field (PCFG.DMASEL) of the Pin Configuration Register.
Page 176: Dynamic Chain Operation
Chapter 8 DMA Controller Initiate DMA transfer Setting the address of the DMA Command Descriptor at the beginning of the chain list in the DMA Chain Address Register (DMCHARn) automatically initiates DMA transfer. First, the value stored in each field of the DMA Command descriptor at the beginning of the Chain List is read to each corresponding DMA Channel register (Chain transfer), then DMA transfer is performed according to the read value.
Page 177: Interrupts
Chapter 8 DMA Controller 8.3.12 Interrupts An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition, there are completion interrupts for when transfer ends normally and error interrupts for when transfer ends abnormally for each channel. When an interrupt occurs, then the bit that corresponds to either the Normal Interrupt Status field (DIS[3:0]) or the Error Interrupt Status field (EIS[3:0]) of the DMA Master Control Register (DMMCR) is set.
Page 178: Arbitration Among Dma Channels
Chapter 8 DMA Controller 8.3.14 Arbitration Among DMA Channels The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the round robin method and the fixed priority method.
Page 179: Dma Controller Registers
Chapter 8 DMA Controller DMA Controller Registers Table 8.4.1 DMA Controller 0 Registers Offset Address Bit Width Mnemonic Register Name 0xB000 DM0CHAR0 DMA Chain Address Register 0 0xB008 DM0SAR0 DMA Source Address Register 0 0xB010 DM0DAR0 DMA Destination Address Register 0 0xB018 DM0CNTR0 DMA Count Register 0...
Page 180 Chapter 8 DMA Controller Table 8.4.2 DMA Controller 1 Registers Offset Address Bit Width Mnemonic Register Name 0xB800 DM1CHAR0 DMA Chain Address Register 0 0xB808 DM1SAR0 DMA Source Address Register 0 0xB810 DM1DAR0 DMA Destination Address Register 0 0xB818 DM1CNTR0 DMA Count Register 0 0xB820 DM1SAIR0...
Page 181: Dma Master Control Register (Dm0Mcr, Dm1Mcr)
Chapter 8 DMA Controller 8.4.1 DMA Master Control Register (DM0MCR, DM1MCR) Offset address: DMAC0 0xB150, DMAC1 0xB950 This register controls the entire DMA Controller. Reserved : Type : Initial value Reserved : Type : Initial value EIS[3:0] DIS[3:0] Reserved FIFVC : Type : Initial value 0000...
Page 182 Chapter 8 DMA Controller Mnemonic Field Name Description Read/Write FIFO Use Enable [3:0] (Default: 0x0) FIFUM[3:0] FIFO Use Enable [3:0] Each channel specifies whether to use 8-double word FIFO in Dual Address transfer. FIFUM[n] corresponds to channel n. Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information.
Page 183: Dma Channel Control Register (Dm0Ccrn, Dm1Ccrn)
Chapter 8 DMA Controller 8.4.2 DMA Channel Control Register (DM0CCRn, DM1CCRn) Offset address: DMAC0 0xB030 (ch. 0) / 0xB070 (ch. 1) / 0xB0B0 (ch. 2) / 0xB0F0 (ch. 3) DMAC1 0xB830 (ch. 0) / 0xB870 (ch.1 ) / 0xB8B0 (ch. 2) / 0xB8F0 (ch. 3) Reserved : Type : Initial value...
Page 184 Chapter 8 DMA Controller Mnemonic Field Name Description Read/Write Destination Burst Inhibit (Default: 0) DBINH Destination Burst Inhibit During Dual Address transfer, this bit sets whether to perform Burst transfer or Single transfer on a Write cycle to the address set from FIFO to DMDARn when Burst transfer is set by DMCCRn.XFSZ.
Page 185 Chapter 8 DMA Controller Mnemonic Field Name Description Read/Write EXTRQ External Request External Request (Default: 0) Sets the Request Transfer mode. 1: I/O DMA transfer mode This bit is used by the External I/O DMA Transfer mode and the Internal I/O DMA Transfer mode.
Page 186 Chapter 8 DMA Controller Mnemonic Field Name Description Read/Write CHNEN Chain Enable Chain Enable (Default: 0) This bit indicates whether Chain operation is being performed. Read Only. This bit is cleared when either the Master Enable bit (DMMCR.MSTEN) is cleared or the Channel Reset bit (DMCCRn.CHRST) is set. This bit is set if a value other than “0”...
Page 187: Dma Channel Status Register (Dm0Csrn, Dm1Csrn))
Chapter 8 DMA Controller 8.4.3 DMA Channel Status Register (DM0CSRn, DM1CSRn)) Offset Address: DMAC0 0xB038 (ch. 0) / 0xB078 (ch. 1) / 0xB0B8 (ch. 2) / 0xB0F8 (ch. 3) DMAC1 0xB838 (ch. 0) / 0xB878 (ch. 1) / 0xB8B8 (ch. 2) / 0xB8F8 (ch. 3) Reserved : Type : Initial value...
Page 188 Chapter 8 DMA Controller Mnemonic Field Name Description Read/Write XFACT Transfer Active Transfer Active (Default: 0) This value is a copy of the Transfer Active bit (XFACT) of the DMA Channel Control Register (DMCCRn). ABCHC Error Complete Error Completion (Default: 0) This bit indicates whether an error occurred during DMA transfer.
Page 189: Dma Source Address Register (Dm0Sarn, Dm1Sarn)
Chapter 8 DMA Controller 8.4.4 DMA Source Address Register (DM0SARn, DM1SARn) Offset Address: DMAC0 0xB008 (ch. 0) / 0xB048 (ch. 1) / 0xB088 (ch. 2) / 0xB0C8 (ch. 3) DMAC1 0xB808 (ch. 0) / 0xB848 (ch. 1) / 0xB888 (ch. 2) / 0xB8C8 (ch. 3) Reserved : Type : Initial value...
Page 190: Dma Destination Address Register (Dm0Darn, Dm1Darn)
Chapter 8 DMA Controller 8.4.5 DMA Destination Address Register (DM0DARn, DM1DARn) Offset Address: DMAC0 0xB010 (ch. 0) / 0xB050 (ch. 1) / 0xB090 (ch. 2) / 0xB0D0 (ch. 3) DMAC1 0xB810 (ch. 0) / 0xB850 (ch. 1) / 0xB890 (ch. 2) / 0xB8D0 (ch. 3) Reserved : Type : Initial value...
Page 191: Dma Chain Address Register (Dm0Charn, Dm1Charn)
Chapter 8 DMA Controller 8.4.6 DMA Chain Address Register (DM0CHARn, DM1CHARn) Offset Address: DMAC0 0xB000 (ch. 0) / 0xB040 (ch. 1) / 0xB080 (ch. 2) / 0xB0C0 (ch. 3) DMAC1 0xB800 (ch. 0) / 0xB840 (ch. 1) / 0xB880 (ch. 2) / 0xB8C0 (ch. 3) Reserved : Type : Initial value...
Page 192: Dma Source Address Increment Register (Dm0Sairn, Dm1Sairn)
Chapter 8 DMA Controller 8.4.7 DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn) Offset Address: DMAC0 0xB020 (ch. 0) / 0xB060 (ch. 1) / 0xB0A0 (ch. 2) / 0xB0E0 (ch. 3) DMAC1 0xB820 (ch. 0) / 0xB860 (ch. 1) / 0xB8A0 (ch. 2) / 0xB8E0 (ch. 3) Reserved : Type : Initial value...
Page 193: Dma Destination Address Increment Register (Dm0Dairn, Dm1Dairn)
Chapter 8 DMA Controller 8.4.8 DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) Offset Address: DMAC0 0xB028 (ch. 0) / 0xB068 (ch. 1) / 0xB0A8 (ch. 2) / 0xB0E8 (ch. 3) DMAC1 0xB828 (ch. 0) / 0xB868 (ch. 1) / 0xB8A8 (ch. 2) / 0xB8E8 (ch. 3) Reserved : Type : Initial value...
Page 194: Dma Count Register (Dm0Cntrn, Dm1Cntrn)
Chapter 8 DMA Controller 8.4.9 DMA Count Register (DM0CNTRn, DM1CNTRn) Offset Address: DMAC0 0xB018 (ch. 0) / 0xB058 (ch. 1) / 0xB098 (ch. 2) / 0xB0D8 (ch. 3) DMAC1 0xB818 (ch. 0) / 0xB858 (ch. 1) / 0xB898 (ch. 2) / 0xB8D8 (ch. 3) Reserved : Type : Initial value...
Page 195: Dma Memory Fiill Data Register (Dm0Mfdr, Dm1Mfdr)
Chapter 8 DMA Controller 8.4.10 DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) Offset Address: DMAC0 0xB148, DMAC1 0xB948 : Type ⎯ : Initial value : Type ⎯ : Initial value : Type ⎯ : Initial value : Type ⎯ : Initial value Mnemonic Field Name Description...
Page 196: Timing Diagrams
Chapter 8 DMA Controller Timing Diagrams This section contains timing diagrams for the external I/O DMA transfer mode. The DMAREQ[n] signals and DMAACK[n] signals in the timing diagrams are set to Low Active. 8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM) SYSCLK ADDR [19:0] 1c040...
Page 197: Single Address Single Transfer From Memory To I/O (16-Bit Rom)
Chapter 8 DMA Controller 8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM) Figure 8.5.2 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 16-bit ROM) 8-41...
Page 198: Single Address Single Transfer From I/O To Memory (32-Bit Sram)
Chapter 8 DMA Controller 8.5.3 Single Address Single Transfer from I/O to Memory (32-bit SRAM) SYSCLK ADDR [19:0] 1c040 00140 ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] 00000100 ACK* DMAREQ[n] DMAACK DMADONE* Figure 8.5.3 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SRAM) 8-42...
Page 199: Single Address Burst Transfer From Memory To I/O (32-Bit Rom)
Chapter 8 DMA Controller 8.5.4 Single Address Burst Transfer from Memory to I/O (32-bit ROM) Figure 8.5.4 Single Address Burst Transfer from Memory to I/O (Burst Read of 4-word Data from 32-bit ROM) 8-43...
Page 200: Single Address Burst Transfer From I/O To Memory (32-Bit Sram)
Chapter 8 DMA Controller 8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM) Figure 8.5.5 Single Address Burst Transfer from I/O to Memory (Burst Write of 4-word Data from 32-bit SRAM) 8-44...
Page 201 Chapter 8 DMA Controller Figure 8.5.6 Single Address Burst Transfer from I/O to Memory (Burst Write of 8-word Data to 32-bit SRAM) 8-45...
Page 202: Single Address Single Transfer From Memory To I/O (16-Bit Rom)
Chapter 8 DMA Controller 8.5.6 Single Address Single Transfer from Memory to I/O (16-bit ROM) SYSCLK ADDR [19:0] 38080 00080 ACE* OE*/BUSSPRT* SWE* BWE* DATA [15:0] 0000 ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.7 Single Address Single Transfer from Memory to I/O (Single Read from 16-bit ROM to 16-bit Data) 8-46...
Page 203: Single Address Single Transfer From I/O To Memory (16-Bit Sram)
Chapter 8 DMA Controller 8.5.7 Single Address Single Transfer from I/O to Memory (16-bit SRAM) Figure 8.5.8 Single Address Single Transfer from I/O to Memory (Single Write of 16-bit Data to 16-bit SRAM) 8-47...
Page 204: Single Address Single Transfer From Memory To I/O (32-Bit Half Speed Rom)
Chapter 8 DMA Controller 8.5.8 Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) Figure 8.5.9 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit Half Speed ROM) 8-48...
Page 205: Single Address Single Transfer From I/O To Memory (32-Bit Half Speed Sram)
Chapter 8 DMA Controller 8.5.9 Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) Figure 8.5.10 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit Half Speed SRAM) 8-49...
Page 206: Single Address Single Transfer From Memory To I/O (64-Bit Sram)
Chapter 8 DMA Controller 8.5.10 Single Address Single Transfer from Memory to I/O (64-bit SRAM) SDCLK ADDR [19:5] 0000 0040 RAS* CAS* CKE* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.11 Single Address Single Transfer from Memory to I/O (Single Read of 64-bit Data from 64-bit SDRAM) 8-50...
Page 207: Single Address Single Transfer From I/O To Memory (64-Bit Sdram)
Chapter 8 DMA Controller 8.5.11 Single Address Single Transfer from I/O to Memory (64-bit SDRAM) SDCLK ADDR [19:5] 0001 0040 RAS* CAS* CKE* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.12 Single Address Single Transfer from I/O to Memory (Single Write of 64-bit Data to 64-bit SDRAM) 8-51...
Page 208: Single Address Single Transfer From Memory To I/O Of Last Cycle When Dmadone* Signal Is Set To Output
Chapter 8 DMA Controller 8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE* Signal is Set to Output SDCLK ADDR [19:5] 0000 0041 RAS* CAS* CKE* OE*/BUSSPRT* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.13 Single Address Single Transfer from Memory to I/O (Single Read of 64-bit Data from 64-bit SDRAM) 8-52...
Page 209: Single Address Single Transfer From Memory To I/O (32-Bit Sdram)
Chapter 8 DMA Controller 8.5.13 Single Address Single Transfer from Memory to I/O (32-bit SDRAM) Figure 8.5.14 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit SDRAM) 8-53...
Page 210: Single Address Single Transfer From I/O To Memory (32-Bit Sdram)
Chapter 8 DMA Controller 8.5.14 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) SDCLK ADDR [19:5] 0002 0080 0081 RAS* CAS* CKE* DQM [7:0] DATA [31:0] 00000100 ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.15 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SDRAM) 8-54...
Page 211: External I/O Device - Sram Dual Address Transfer
Chapter 8 DMA Controller 8.5.15 External I/O Device – SRAM Dual Address Transfer SYSCLK CE* (SRAM) CE* (I/O device) ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31 : 0] Valid Valid Valid Valid Valid Valid Valid Valid ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.16 Dual Address Transfer from External I/O Device to SRAM (8-word Burst Transfer to 32-bit Bus SRAM)
Page 212 Chapter 8 DMA Controller SYSCLK CE* (SRAM) CE* (I/O device) ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] Valid Valid Valid Valid ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.17 Dual Address Transfer from SRAM to External I/O Device (4-word Burst Transfer from 32-bit Bus SRAM) 8-56...
Page 213: External I/O Device - Sdram Dual Address Transfer
Chapter 8 DMA Controller 8.5.16 External I/O Device – SDRAM Dual Address Transfer SDCLK/SYSCLK ADDR [19:0] RAS* CAS* OE*/BUSSPRT* DQM[7:0] DATA [31:0] Valid ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.18 Dual Address Transfer from External I/O Device to SDRAM (4-word Burst Transfer to 32-bit SDRAM) 8-57...
Page 214 Chapter 8 DMA Controller SDCLK/SYSCLK ADDR [19:0] RAS* CAS* OE*/BUSSPRT* DQM[7:0] DATA [31:0] Valid Valid Valid Valid Valid Valid Valid Valid ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.19 Dual Address Transfer from SDRAM to External I/O Device (8-word Burst Transfer from 32-bit SDRAM) 8-58...
Page 215: External I/O Device (Non-Burst) - Sdram Dual Address Transfer
Chapter 8 DMA Controller 8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer SDCLK/SYSCLK ADDR[19:0] RAS* CAS* OE*/ BUSSPRT* DQM[7:0] DATA[31:0] Valid V V V ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.20 Dual Address Transfer from External I/O Device (Non-Burst) to SDRAM (4-word Burst Transfer to 32-bit SDRAM: Set DMCCRn.SBINH to “1”) 8-59...
Page 216 Chapter 8 DMA Controller SDCLK/SYSCLK ADDR[19:0] RAS* CAS* OE*/BUSSPRT* DQM[7:0] DATA[31:0] V V V V Valid Valid Valid Valid ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.21 Dual Address Transfer from SDRAM to External I/O Device (4-word Burst Transfer from 32-bit SDRAM: Set DMCCRn.DBINH to “1”) 8-60...
Page 217: Sdram Controller
Chapter 9 SDRAM Controller SDRAM Controller Characteristics The SDRAM Controller (SDRAMC) generates the control signals required to interface with the SDRAM. There are a total of four channels, which can each be operated independently. The SDRAM Controller supports various bus configurations and a memory size of up to 2 GB. The SDRAM has the following characteristics.
Page 218: Block Diagram
Chapter 9 SDRAM Controller Block Diagram SDRAMC SDCS [3 : 0] * Channel 0 – 7 Control Register G-Bus I/F Signal RAS* Timing Register Control Circuit CAS* G-Bus Interface DQM [7 : 0] Command/Load Control Register Refresh Counter EBIF Control Signal Control Signal G-Bus I/FSignal...
Page 219: Detailed Explanation
Chapter 9 SDRAM Controller Detailed Explanation 9.3.1 Supported SDRAM configurations This controller supports the SDRAM configurations listed below in Table 9.3.1. The MW field of the SDRAM Channel Control Register (SDCCRn) can be used to separately set the data bus width for each channel to either 64 bits or 32 bits. DATA[31:0] and DQM[3:0] are used when using a 32-bit data bus.
Page 220: Address Mapping
Chapter 9 SDRAM Controller 9.3.2 Address Mapping 9.3.2.1 Physical Address Mapping It is possible to map each of the four channels to an arbitrary physical address using the Base Address field (SDCCRn.BA[35:21]) of the SDRAM Channel Control Register and the Address Mask Field (SDCCRn.AM[35:21]).
Page 221 Chapter 9 SDRAM Controller 9.3.2.2 Address Signal Mapping (64-bit Data Bus) Table 9.3.2 shows the address signal mapping when using a 64-bit data bus. B0 is used in the bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection in memory with a four-bank configuration.
Page 222 Chapter 9 SDRAM Controller Table 9.3.2 Address Signal Mapping (64-bit Data Bus) (2/2) Row Address Width = 12 Column Address Width = 11 Address Bit ADDR [19:5] (B0) (B1) (AP) Column Address Row Address Row Address Width = 13 Column Address Width = 8 Address Bit ADDR [19:5] (B0)
Page 223 Chapter 9 SDRAM Controller 9.3.2.3 Address Signal Mapping (32-bit Data Bus) Table 9.3.3 shows the address signal mapping when using a 32-bit data bus. B0 is used in the bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection in memory with a four-bank configuration.
Page 224 Chapter 9 SDRAM Controller Table 9.3.3 Address Signal Mapping (32-bit Data Bus) (2/2) Row Address Width = 12 Column Address Width = 11 Address Bit ADDR [19:5] (B0) (B1) (AP) Column Address Row Address Row Address Width = 13 Column Address Width = 8 Address Bit ADDR [19:5] (B0)
Page 225: Initialization Of Sdram
Chapter 9 SDRAM Controller 9.3.3 Initialization of SDRAM The TX4937 Command Register has functions for generating the cycles required for initializing SDRAM. Using software to set each register makes it possible to execute initial settings at a particular timing. Set the SDRAM Channel Control Register (SDCCRn). Set the SDRAM Timing Register (SDCTR).
Page 226: Initialization Of Memory Data, Ecc/Parity
Chapter 9 SDRAM Controller 9.3.4 Initialization of Memory Data, ECC/Parity The SDRAMC has functions for simultaneously performing Memory Writes to multiple memory channels. These functions are effective when quickly initializing data memory or ECC/parity memory. Channels for which both the Channel Enable bit (SDCCRn.CE) and the Master Enable bit (SDCCRn.ME) of the SDRAM Channel Control Register are set become the Master channel.
Page 227: Low Power Consumption Function
Chapter 9 SDRAM Controller 9.3.5 Low Power Consumption Function 9.3.5.1 Power Down Mode, Self-Refresh Mode SDRAM has two low power consumption modes called the Power Down mode and the Self- Refresh mode. Memory data is lost in the case of the Power Down mode since Memory Refresh is not performed, but the amount of power consumed is reduced the most.
Page 228: Bus Errors
Chapter 9 SDRAM Controller 9.3.6 Bus Errors The SDRAMC detects bus errors in the following situations: • Bus time-out occurs during Read or Write operation to the SDRAMC • ECC 2-bit fault error or Parity error occurs during SDRAM Read operation If a bus error occurs when accessing the SDRAMC, then the SDRAMC will immediately assert the current operation.
Page 229: Ecc
Chapter 9 SDRAM Controller 9.3.10 9.3.10.1 ECC/Parity Mode Table 9.3.5 shows the supported ECC/Parity functions. The ECC/Parity mode can be set separately for each channel using the ECC/Parity Mode field (SDCCRn.ECC) of the SDRAM Channel Control Register. The ECC enable bit (ECCCR.ECCE) of the ECC Control Register must be set in order to use the ECC function.
Page 230 Chapter 9 SDRAM Controller 9.3.10.2 ECC Error Notification When either an ECC error or a parity error occurs, error data is written into one of the following fields, then error notification is performed as described below: • Error Address Field (ERRAD) in the ECC Status Register (ECCSR) •...
Page 231 Chapter 9 SDRAM Controller 9.3.10.3 Adding Read Latency for Each ECC/Parity Mode When using the ECC/parity function, memory access latency is added according to which ECC/parity mode is selected, whether errors will be generated or not, the error type to be generated, and whether or not to generate bus errors.
Page 232 Chapter 9 SDRAM Controller 9.3.10.4 ECC Memory Access 8-bit check code is used whether the data bus width is 64 bits or 32 bits. For 32-bit data bus width, check code is generated for and the error check is performed on 64-bit data that consists of two 32-bit data at the double word boundary.
Page 233: Registers
Chapter 9 SDRAM Controller Registers Table 9.4.1 SDRAM Control Register Offset Address Bit Width Register Symbol Register Name 0x8000 SDCCR0 SDRAM Channel Control Register 0 0x8008 SDCCR1 SDRAM Channel Control Register 1 0x8010 SDCCR2 SDRAM Channel Control Register 2 0x8018 SDCCR3 SDRAM Channel Control Register 3 0x8040...
Page 234: 0X8018 (Ch. 3)
Chapter 9 SDRAM Controller 9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1) 0x8010 (ch. 2) 0x8018 (ch. 3) When the SDCCRn is programmed using a sequence of 32-bit store instructions, the base address and the address mask in the high-order 32-bit portion of the register must be written first, followed by the Channel Enable bit in the low-order 32-bit portion.
Page 235 Chapter 9 SDRAM Controller Mnemonic Field Name Description Read/Write Registered DIMM Registered DIMM (Default: 0) Specifies whether the SDRAM connected to the channel is Registered memory. 0: Disable Registered memory 1: Enable Registered memory ⎯ 14:13 — — Reserved Master Enable Master Enable (Default: 0) Specifies during ECC initialization whether a channel will be made the Master channel.
Page 236: Sdram Timing Register (Sdctr) 0X8040
Chapter 9 SDRAM Controller 9.4.2 SDRAM Timing Register (SDCTR) 0x8040 Reserved :Type :Initial value Reserved :Type :Initial value PDAE CASL R/W :Type :Initial value Reserved :Type 0x30C :Initial value Mnemonic Field Name Description Read/Write ⎯ 63:34 — — Reserved 33:32 Write Active Data In to Active(t ) (Default: 11)
Page 237 Chapter 9 SDRAM Controller Mnemonic Field Name Description Read/Write Advanced CKE Advanced CKE enable (Default: 0) Enabling this function makes the timing at which CKE changes one cycle earlier. 0: Disable 1: Enable Power Down PDAE Power Down Auto Entry Enable (Default: 0) Auto Entry Enabling this function makes CKE become “L”...
Page 238: Sdram Command Register (Sdccmd) 0X8058
Chapter 9 SDRAM Controller 9.4.3 SDRAM Command Register (SDCCMD) 0x8058 Reserved :Type :Initial value Reserved :Type :Initial value MDLNO VERNO :Type 0x30 0x10 :Initial value Reserved :Type :Initial value Mnemonic Field Name Description Read/Write ⎯ 63:32 — — Reserved 31:24 MDLNO Model Number Model Number (Default: 0x30)
Page 239: Ecc Control Register (Ecccr) 0Xa000
Chapter 9 SDRAM Controller 9.4.4 ECC Control Register (ECCCR) 0xA000 MDLNO VERNO 0x10 0x10 :Type :Initial value Reserved :Type :Initial value DECC Reserved R/W :Type :Initial value Reserved Reserved ECCE R/W :Type :Initial value Mnemonic Field Name Description Read/Write 63:56 MDLNO Model Number Model Number (Default: 0x10)
Page 240 Chapter 9 SDRAM Controller Mnemonic Field Name Description Read/Write Single-Bit Error Single-Bit Error Interrupt Enable (Default: 0) Interrupt Enable Specifies whether to generate an interrupt during a single-bit error. 0: Disable 1: Enable ⎯ — — Reserved ECCE ECC Enable ECC Enable (Default: 0) Specifies whether to enable the ECC/Parity function.
Page 241: Ecc Status Register (Eccsr) 0Xa008
Chapter 9 SDRAM Controller 9.4.5 ECC Status Register (ECCSR) 0xA008 ERRAD :Type — — — — — — — — — — — — — — — — :Initial value ERRAD :Type — — — — — — — — —...
Page 242: Timing Diagrams
Chapter 9 SDRAM Controller Timing Diagrams Please note the following when referring to the timing diagrams in this section: the shaded area each diagram expresses values that have yet to be determined. 9.5.1 Single Read (64-bit Bus) SDCLK SDCS* ADDR 7fff 0000 [19:5]...
Page 243 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 7fff 0000 RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* = 3, t = 3, t = 1, 64-bit Bus) Figure 9.5.2 Single Read (t CASL 9-27...
Page 244: Single Write (64-Bit Bus)
Chapter 9 SDRAM Controller 9.5.2 Single Write (64-bit Bus) SDCLK SDCS* 0000 0400 ADDR [19:5] RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* = 2, t = 0, 64-bit Bus) Figure 9.5.3 Double-Word Single Write (t 9-28...
Page 245 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* = 3, t = 1, 64-bit Bus) Figure 9.5.4 One-Word Single Write (t 9-29...
Page 246: Burst Read (64-Bit Bus)
Chapter 9 SDRAM Controller 9.5.3 Burst Read (64-bit Bus) = 2, t = 2, t = 0, 64-bit Bus) Figure 9.5.5 Eight-Word Burst Read (t CASL 9-30...
Page 247: Burst Write (64-Bit Bus)
Chapter 9 SDRAM Controller 9.5.4 Burst Write (64-bit Bus) = 2, t = 0, 64-bit Bus) Figure 9.5.6 Eight-Word Burst Write (t 9-31...
Page 248: Burst Write (64-Bit Bus, Slow Write Burst)
Chapter 9 SDRAM Controller 9.5.5 Burst Write (64-bit Bus, Slow Write Burst) = 2, t = 0, 64-bit Bus, Slow Write Burst) Figure 9.5.7 Eight-Word Burst Write (t 9-32...
Page 249: Single Read (32-Bit Bus)
Chapter 9 SDRAM Controller 9.5.6 Single Read (32-bit Bus) SDCLK SDCS* ADDR 7fff 0000 [19:5] RAS* CAS* DQM [7:0] DATA [31:0] CB [7:0] ACK*/READY* = 2, t = 2, t = 0, 32-bit Bus) Figure 9.5.8 Double-Word Single Read (t CASL 9-33...
Page 250 Chapter 9 SDRAM Controller SDCLK SDCS* 7fff 0000 ADDR [19:5] RAS* CAS* DQM [7:0] DATA [31:0] CB [7:0] ACK*/READY* = 2, t = 3, t = 0, 32-bit Bus) Figure 9.5.9 One-Word Single Read (t CASL 9-34...
Page 251: Single Write (32-Bit Bus)
Chapter 9 SDRAM Controller 9.5.7 Single Write (32-bit Bus) SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* = 2, t = 0, 32-bit Bus) Figure 9.5.10 Double-Word Single Write (t 9-35...
Page 252 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* = 3, t = 0, 32-bit Bus) Figure 9.5.11 One-Word Single Write (t 9-36...
Page 253: Low Power Consumption And Power Down Mode
Chapter 9 SDRAM Controller 9.5.8 Low Power Consumption and Power Down Mode SDCLK SDCS* ADDR [19:5] RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* Figure 9.5.12 Transition to Low Power Consumption Mode (SDCTR.ACE = 0) 9-37...
Page 254 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* Figure 9.5.13 Transition to Power Down Mode 9-38...
Page 255 Chapter 9 SDRAM Controller Figure 9.5.14 Return From Low Power Consumption/Power Down Mode (SDCTR.PDAE = 0, SDCTR.ACE = 0) 9-39...
Page 256 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR 0000 0400 [19:5] RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* Figure 9.5.15 Power Down Auto Entry (SDCTR.PDAE = 1, SDCTR.ACE = 0) 9-40...
Page 257 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:18] SDCSFCMD.BK ADDR [17:12] ADDR [12:5] SDCSFCMD.CMD RAS* CAS* DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY Figure 9.5.16 LCR Command 9-41...
Page 258: Sdram Usage Example
Chapter 9 SDRAM Controller SDRAM Usage Example Figure 9.6.1 illustrates an example SDRAM connection. Figure 9.6.2 illustrates an example SDRAM DIMM (168-pin) connection. TX4937 SDRAM (×16 bits) DQM [7] DQM [6] DQM [5] DQM [4] DQM [3] DQM [2] DQM [1] DQM [0] DQM [7:0] UDQM LDQM UDQM LDQM...
Page 259: Pci Controller
Chapter 10 PCI Controller 10. PCI Controller 10.1 Features The TX4937 PCI Controller functions as a bus bridge between the TX4937 External PCI and the internal bus (G-Bus). 10.1.1 Overall • Compliant to “PCI Local Bus Specification Revision 2.2” • PCI Bus: 32-bit data bus;...
Page 260: Target Function
Chapter 10 PCI Controller 10.1.3 Target Function • Single and Burst transfer from the PCI Bus to the Internal Bus • Supports memory, I/O, and configuration cycles • Supports high-speed back-to-back transactions on the PCI Bus • Address mapping between the PCI Bus and the Internal bus can be modified •...
Page 261: Block Diagram
Chapter 10 PCI Controller 10.2 Block Diagram TX49/H3 Core Memory Controller DMA Controller Arbiter G-Bus PCI Controller Retry G-Bus I/F Targ. cont. Mast. cont. PDMAC (64-bit × 4) (PCI→G-Bus) (G-Bus→PCI) 64-bit × 4 Config EBUSC Arb. Req. × 4 Target Target Master Master...
Page 262: Detailed Explanation
Chapter 10 PCI Controller 10.3 Detailed Explanation 10.3.1 Terminology Explanation The following terms are used in this chapter. • Initiator Means the bus Master of the PCI Bus. The TX4937 operates as the initiator when it obtains the PCI Bus and issues PCI access. •...
Page 263 Chapter 10 PCI Controller Registers in the PCI Controller Control Register that include an offset address in the range from 0xD000 to 0xD07F can only be accessed when in the Host mode and cannot be accessed when in the Satellite mode. These registers correspond to PCI Configuration Space Registers that an external PCI Host device accesses when in the Satellite mode.
Page 264: Supported Pci Bus Commands
Chapter 10 PCI Controller 10.3.3 Supported PCI Bus Commands Table 10.3.1 shows the PCI Bus commands that the PCI Controller supports. Table 10.3.1 Supported PCI Bus Commands C/BE Value PCI Command As Initiator As Target ⎯ 0000 Interrupt Acknowledge † ⎯...
Page 265 Chapter 10 PCI Controller The Memory Read command is issued if these conditions are not met, namely, if “0” is set to the Cache Line Size field (PCICFG1.CLS) of the PCI Configuration 1 Register. In the case of the target, a normal G-Bus cycle is issued to the address mapped from the PCI Bus to the G-Bus. •...
Page 266: Initiator Access (G-Bus → Pci Bus Address Conversion)
Chapter 10 PCI Controller Configuration cycles will be accepted as the target only when in the Satellite mode. After reset, Retry response to PCI Configuration access will continue until the software sets the Target Configuration Access Ready Bit (PCICFG.TCAR) of the PCI Controller Configuration Register. Please use the software to set this bit after the software initialization process ends and the software is ready to accept PCI configuration.
Page 267 Chapter 10 PCI Controller When expressed as a formula, conversion of a G-Bus address (GBusAddr[35:0]) into a PCI Bus Address (PCIAddr[39:0]) is as follows below. GBASE[35:8], PBASE[39:8], and AM[35:8] each represent the setting register of the corresponding access window indicated below in Table 10.3.2. The “&”...
Page 268: Target Access (Pci Bus → G-Bus Address Conversion)
Chapter 10 PCI Controller Table 10.3.3 Initiator Access Space Properties Register Enable Word Swap Memory Space 0 BusMasterEnable & PCICCFG.G2PM0EN G2PM0GBASE.BSWAP Memory Space 1 BusMasterEnable & PCICCFG.G2PM1EN G2PM1GBASE.BSWAP Memory Space 2 BusMasterEnable & PCICCFG.G2PM2EN G2PM2GBASE.BSWAP I/O Space BusMasterEnable & PCICCFG.G2PIOEN G2PIOGBASE.BSWAP BusMasterEnable: Host mode:...
Page 269 Chapter 10 PCI Controller When expressed as a formula, conversion of a PCI Bus Address (PCIAddr[39:0]) into a G-Bus address (GBusAddr[35:0]) is as follows below. GBASE[35:8], and PBASE[39:8] each represent the setting register of the corresponding access window indicated below in Table 10.3.4. The “&” symbol indicates a logical AND for each bit, and “|”...
Page 270: Post Write Function
Chapter 10 PCI Controller It is possible to set each space to valid/invalid, pre-fetch Read to valid/invalid, or to perform Word Swap (see10.3.7). Table 10.3.5 shows the settings registers for these properties. When pre-fetch Reads are set to valid, data transfer is performed on the G-Bus according to the size set by the Target Pre-fetch Read Burst Length Field (P2GCFG.TPRBL) of the P2G Configuration Register during a PCI target Read transaction.
Page 271: 66 Mhz Operation Mode
Chapter 10 PCI Controller Initial state operation matches the correspondence between the address and byte data regardless of the endian mode (operation is address consistent). For example, if WORD (16-bit) data is written to address 0 of the PCI Bus when the TX4937 is in the Big Endian mode, the upper byte (address 0 in Big Endian) is written to PCI Bus address 0 and the lower byte (address 1 in Big Endian) is written to address 1 of the PCI Bus.
Page 272: Power Management
Chapter 10 PCI Controller PCI Reset is detected by either using the PCI Bus Reset Signal as the TX4937 overall reset signal or using the PCI Bus Reset Signal assertion detection device that the system provides. Then, the software reset the PCI Controller. The software uses a hardware reset (PCICCFG.HRST) of the PCI Controller Configuration Register to reset the PCI Controller.
Page 273: Pdmac (Pci Dma Controller)
Chapter 10 PCI Controller 10.3.9.2 PME* Signal (Satellite Mode) The following PMEs (Power Management Events) are reported when in the Satellite mode. • The PCI Host device sets the PME_En bit of the PMCSR Register in the TX4937 Configuration space. This makes it possible for the TX4937 to assert the PME* signal. Then, the PME_En Set bit (P2GSTATUS.PMEES) of the P2G Status Register is set.
Page 274 Chapter 10 PCI Controller PDMAC Status Register (PDMSTATUS) Clearing Clears any remaining status from a previous DMA transfer. PDMAC Configuration register (PDMCFG) Setting Clears the Channel Reset bit (CHRST), and makes settings such as the data transfer direction (XFRDIRC), and the data transfer unit size (XFRSIZE). DMA Transfer Initiation Setting the Transfer Active bit (XFRACT) of the PDMAC Configuration Register initiates DMA transfer.
Page 275 Chapter 10 PCI Controller The DMA transfer procedure is as follows when in the Chain DMA mode. Count Register Setting Sets “0” to the PDMAC Count Register (PMDCTR). DMA Command Descriptor Chain Construction Constructs the DMA Command Descriptor Chain in memory. PDMAC Status Register (PDMSTATUS) Clearing Clears any remaining status from a previous DMA transfer.
Page 276: Error Detection, Interrupt Reporting
Chapter 10 PCI Controller 10.3.10.3 Dynamic Chain Operation It is possible to dynamically add other DMA Command Descriptor Chains to a DMA Command Descriptor Chain that is currently being processed when executing DMA data transfer. This is done according to the following procedure. DMA Command Descriptor Chain Construction Constructs a DMA Command Descriptor Chain in memory.
Page 277 Chapter 10 PCI Controller 10.3.11.2 PDMAC Interrupts Name Status Bit Interrupt Enable Bit Normal Chain Termination NCCMP NCCMPIE Normal Data Transfer Termination NTCMP NTCMPIE STLTRF Inter-Transfer Stall Time Reached PDMSTATUS PDMCFG Configuration Error CFGERR ERRIE PCI Fatal Error PCIERR CHNERR G-Bus Chain Error G-Bus Data Error DATAERR...
Page 278: Pci Bus Arbiter
Chapter 10 PCI Controller 10.3.12 PCI Bus Arbiter Configuration settings (DATA[2] signal) during boot up select whether to use the on-chip PCI Bus arbiter (Internal PCI Bus Arbiter mode) or to use the External PCI Bus arbiter (External PCI Bus Arbiter mode).
Page 279 Chapter 10 PCI Controller The Bus Master priority is determined based on the Level 1 round-robin sequence. However, when Level 2 is used inside Level 1, the Level 2 Bus Master priority is determined based on the Level 2 round-robin sequence. All 8 Bus Masters cannot be used on the TX4937.
Page 280: Pci Boot
Chapter 10 PCI Controller 10.3.12.5 Special Programming There may be some devices among PCI bus masters that operate differently from typical PCI devices. PCI devices with the following characteristics can be made usable by changing the programming of the PCI bus arbiter. Bus masters that can not re-assert REQ unless GNT is once deasserted after deasserting REQ •...
Page 281: Set Configuration Space
Chapter 10 PCI Controller 10.3.14 Set Configuration Space In Table 10.5.1, the values for the registers inside the PCI Configuration Space Register that have a gray background can be rewritten using one of the two following methods. 10.3.14.1 Set the Configuration Space Using EEPROM Load values during Reset by connecting standard 93C46/93C48 EEPROM to a dedicated port.
Page 282: Pci Controller Control Register
Chapter 10 PCI Controller 10.4 PCI Controller Control Register Table 10.4.1 lists the registers contained in the PCI Controller Control Register. Parentheses in the register names indicate the corresponding PCI Configuration Space Register. Table 10.4.1 PCI Controller Control Register (1/2) Section Address Size...
Page 283 Chapter 10 PCI Controller Table 10.4.1 PCI Controller Control Register (2/2) Section Address Size Mnemonic Register Name 10.4.41 0xD160 G2PM2PBASE G2P Memory Space 2 PCI Base Address Register 10.4.42 0xD168 G2PIOPBASE G2P I/O Space PCI Base Address Register 10.4.43 0xD170 PCICCFG PCI Controller Configuration Register 10.4.44...
Page 284: Id Register (Pciid) 0Xd000
Chapter 10 PCI Controller 10.4.1 ID Register (PCIID) 0xD000[HH5] The Device ID field corresponds to the Device ID Register in the PCI Configuration Space, and the Vendor ID field corresponds to the Vendor ID register of the PCI Configuration Space. This register cannot be access when in the Satellite mode.
Page 285: Pci Status, Command Register (Pcistatus) 0Xd004
Chapter 10 PCI Controller 10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004 The upper 16 bits correspond to the Status Register in the PCI Configuration Space, and the lower 16 bits correspond to the Command Register in the PCI Configuration Space. This register cannot be accessed when in the Satellite mode.
Page 286 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write Master Data MDPE Master Data Parity Error (Default: 0) R/W1C Parity Error Indicates the a parity error occurred when the PCI Controller is the PCI initiator. This bit is not set when the PCI Controller is the target. This bit is set when all of the three following conditions are met.
Page 287 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write MEMSP Memory Space Memory Space (Default: 0) 1: Respond to PCI memory access. 0: Do not respond to PCI memory access. IOSP I/O Space I/O Space (Default: 0) 1: Respond to PCI I/O access. 0: Do not respond to PCI I/O access.
Page 288: Class Code, Revision Id Register (Pciccrev) 0Xd008
Chapter 10 PCI Controller 10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008 The Class Code field corresponds to the Class Code Register of the PCI Configuration Space, and the Revision ID field corresponds to the Revision ID Register of the PCI Configuration Space. This register cannot be accessed when in the Satellite mode.
Page 289: Pci Configuration 1 Register (Pcicfg1) 0Xd00C
Chapter 10 PCI Controller 10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C The following fields correspond to the following registers. BIST field → BIST Register of the PCI Configuration Space Header Type field → Header Type Register in the PCI Configuration Space Latency Timer field →...
Page 290: P2G Memory Space 0 Pci Lower Base Address Register (P2Gm0Plbase) 0Xd010
Chapter 10 PCI Controller 10.4.5 P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0xD010 This register corresponds to the Memory Space 0 Lower Base Address Register at offset address 0x10 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. BA[31:29] Reserved : Type...
Page 291: P2G Memory Space 0 Pci Upper Base Address Register (P2Gm0Pubase) 0Xd014
Chapter 10 PCI Controller 10.4.6 P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0xD014 This register is unused since the PCI Controller does not support the target dual-address cycle. It is forbidden to write to this register. 10.4.7 P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0xD018 This register corresponds to the Memory Space 1 Lower Base Address Register at offset address 0x18 of the PCI Configuration Space.
Page 292: P2G Memory Space 1 Pci Upper Base Address Register (P2Gm1Pubase) 0Xd01C
Chapter 10 PCI Controller 10.4.8 P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0xD01C This register is unused since the PCI Controller does not support the target dual-address cycle. It is forbidden to write to this register. 10.4.9 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD020 This register corresponds to the Memory Space 2 Base Address Register at offset address 0x20 of the...
Page 293: P2G I/O Space Pci Base Address Register (P2Giopbase) 0Xd024
Chapter 10 PCI Controller 10.4.10 P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD024 This register corresponds to the I/O Space Base Address at offset address 0x24 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. BA[31:16] : Type 0x0000...
Page 294: Subsystem Id Register (Pcisid) 0Xd02C
Chapter 10 PCI Controller 10.4.11 Subsystem ID Register (PCISID) 0xD02C The Subsystem ID field corresponds to the Subsystem ID Register of the PCI Configuration Space, and the Subsystem Vendor ID field corresponds to the Subsystem Vendor ID Register of the PCI Configuration Space.
Page 295: Capabilities Pointer Register (Pcicapptr) 0Xd034
Chapter 10 PCI Controller 10.4.12 Capabilities Pointer Register (PCICAPPTR) 0xD034 The Capabilities Pointer field corresponds to the Capabilities Pointer Register of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. Reserved : Type : Initial value Reserved...
Page 296: Pci Configuration 2 Register (Pcicfg2) 0Xd03C
Chapter 10 PCI Controller 10.4.13 PCI Configuration 2 Register (PCICFG2) 0xD03C The following fields correspond to the following registers: Max. Latency field → Max_Lat Register of the PCI Configuration Space Min. Grant field → Min_Gnt Register of the PCI Configuration Space Interrupt Pin field →...
Page 297: G2P Timeout Count Register (G2Ptocnt) 0Xd040
Chapter 10 PCI Controller 10.4.14 G2P Timeout Count Register (G2PTOCNT) 0xD040 The Retry Timeout field corresponds to the Retry Timeout Value Register of the PCI Configuration Space, and the TRDY Timeout field corresponds to the TRDY Timeout Value Register of the PCI Configuration Space.
Page 298: G2P Status Register (G2Pstatus) 0Xd080
Chapter 10 PCI Controller 10.4.15 G2P Status Register (G2PSTATUS) 0xD080 Reserved : Type : Initial value Reserved IDTTOE IDRTOE : Type R/W1C R/W1C 0x0 : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:2 Reserved IDTTOE TRDY Timeout Initiator Detected TRDY Time Out Error (Default: 0x0) R/W1C Error This bit is set when the initiator detects a TRDY timeout.
Page 299: G2P Interrupt Mask Register (G2Pmask) 0Xd084
Chapter 10 PCI Controller 10.4.16 G2P Interrupt Mask Register (G2PMASK) 0xD084 Reserved : Type : Initial value Reserved IDTTOEIE IDRTOEIE R/W : Type 0x0 : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:2 Reserved IDTTOEIE TRDY Timeout Initiator Detected TRDY Time Out Interrupt Enable (Default: 0x0) Error Interrupt The initiator generates an interrupt when it detects a TRDY timeout.
Page 300: Satellite Mode Pci Status Register (Pcisstatus) 0Xd088
Chapter 10 PCI Controller 10.4.17 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088 The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to read values from either of these registers.
Page 301: Pci Status Interrupt Mask Register (Pcimask) 0Xd08C
Chapter 10 PCI Controller 10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C Reserved : Type : Initial value DPEIE SSEIE RMAIE RTAIE STAIE Reserved Reserved MDPEIE : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:16 Reserved DPEIE Detected Parity Detected Parity Error Interrupt Enable (Default: 0x0) Error Interrupt...
Page 302: P2G Configuration Register (P2Gcfg) 0Xd090
Chapter 10 PCI Controller 10.4.19 P2G Configuration Register (P2GCFG) 0xD090 Reserved TPRBL Reserved R/W1S : Type : Initial value FTRD TOBFR TIBFR Reserved Reserved MEM0PD MEM1PD MEM2PD : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:23 Reserved PME (Default: 0x0) R/W1S When the PCI Controller is in the Satellite mode, writing “1”...
Page 303 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write MEM1PD Memory 1 Memory 1 Window Prefetch Disable (Default: 0x0) Window Prefetch Prefetching during a G-Bus Burst Read transfer cycle to the Memory 1 Disable Space is disabled when this bit is set to “1”. PCI Burst Read transactions are not supported when prefetching is disabled.
Page 304: P2G Status Register (P2Gstatus) 0Xd094
Chapter 10 PCI Controller 10.4.20 P2G Status Register (P2GSTATUS) 0xD094 Reserved PMSC M66EN IOBFE IIBFE TOBFE TIBFE PMEES PMECLR Reserved R/W1C R/W1C R/W1C : Type : Initial value Reserved : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:25 Reserved PM State Change...
Page 305: P2G Interrupt Mask Register (P2Gmask) 0Xd098
Chapter 10 PCI Controller 10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098 Reserved Reserved PMSCIE PMEESIE M66ENIE PMECLRIE : Type : Initial value Reserved : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:25 Reserved Power PMSCIE Power Management State Change Interrupt Enable (Default: 0x0) Management Generates an interrupt when the PowerState field of the Power State Change...
Page 306: P2G Current Command Register (P2Gccmd) 0Xd09C
Chapter 10 PCI Controller 10.4.22 P2G Current Command Register (P2GCCMD) 0xD09C Reserved : Type : Initial value Reserved TCCMD : Type : Initial value Bits Mnemonic Field Name Description Read/Write ⎯ 31:4 Reserved Target Current TCCMD Target Current Command (Default: 0x0) Command Indicates the PCI command within the target access process that is Register...
Page 307: Pci Bus Arbiter Request Port Register (Pbareqport) 0Xd100
Chapter 10 PCI Controller 10.4.23 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100 This register sets the correlation between each PCI Bus request source (PCI Controller and REQ[3:0]) and each Internal PCI Bus Arbiter Request port (Master A - D, W - Z) (see Figure 10.3.8). When changing the settings of this register, unused ports must be programmed to a reserved value.
Page 308 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write ⎯ Reserved 18:16 ReqDP Request D Port Request D Port (Default: 100) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request D Port (Master D). 111: Makes the PCI Controller Master D. 110: Reserved 101: Reserved 100: Reserved...
Page 309: Pci Bus Arbiter Configuration Register (Pbacfg) 0Xd104
Chapter 10 PCI Controller 10.4.24 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 This register is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved FIXPA RPBA PBAEN BMCEN R/W : Type : Initial value Mnemonic Field Name Description...
Page 310 Chapter 10 PCI Controller 10.4.25 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 This register is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved R/W1C : Type : Initial value Mnemonic Field Name Description Read/Write ⎯...
Page 311: Pci Bus Arbiter Interrupt Mask Register (Pbamask) 0Xd10C
Chapter 10 PCI Controller 10.4.26 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C This register is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved BMIE R/W : Type : Initial value Mnemonic Field Name Description Read/Write...
Page 312: Pci Bus Arbiter Broken Master Register (Pbabm) 0Xd110
Chapter 10 PCI Controller 10.4.27 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 This register indicates the acknowledged Broken Master. This register sets the bit that corresponds to the PCI Master device that was acknowledged as the Broken Master when the Broken Master Check Enable bit (BMCEN) in the PCI Bus Arbiter Configuration Register (PBACFG) is set.
Page 313 Chapter 10 PCI Controller 10.4.28 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 This register is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved CPCIBRS : Type 0x00 : Initial value Bits...
Page 314: Pci Bus Arbiter Current Grant Register (Pbacgnt) 0Xd118
Chapter 10 PCI Controller 10.4.29 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 This is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved CPCIBGS : Type 0x80 : Initial value Bits Mnemonic...
Page 315: Pci Bus Arbiter Current State Register (Pbacstate) 0Xd11C
Chapter 10 PCI Controller 10.4.30 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C This is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved Reserved CPAS : Type 0x00 : Initial value Mnemonic...
Page 316 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write Current PCI Bus CPAS Current PCI Bus Arbiter State (Default: 0x00) Arbiter State Displays the State Machine that was selected by the FSM bit. Please refer to Figures 12.5.3 and 12.11.1 for an explanation of Agent/Grant A - W and Level 2.
Page 317: G2P Memory Space 0 G-Bus Base Address Register (G2Pm0Gbase) 0Xd120
Chapter 10 PCI Controller 10.4.31 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00...
Page 318: G2P Memory Space 1 G-Bus Base Address Register (G2Pm1Gbase) 0Xd128
Chapter 10 PCI Controller 10.4.32 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00...
Page 319: G2P Memory Space 2 G-Bus Base Address Register (G2Pm2Gbase) 0Xd130
Chapter 10 PCI Controller 10.4.33 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0xD130 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:16] : Type 0x0000/0x1FC0 : Initial value BA[15:8] Reserved : Type 0x00...
Page 320: G2P I/O Space G-Bus Base Address Register (G2Piogbase) 0Xd138
Chapter 10 PCI Controller 10.4.34 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0xD138 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 0x00...
Page 321: G2P Memory Space 0 Address Mask Register (G2Pm0Mask) 0Xd140
Chapter 10 PCI Controller 10.4.35 G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0xD140 AM[35:20] : Type 0x0000 : Initial value AM[19:8] Reserved : Type 0x000 : Initial value Mnemonic Field Name Description Read/Write 31:4 AM[35:8] Address Mask G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) Sets the bits to be subject to address comparison.
Page 322: G2P Memory Space 1 Address Mask Register (G2Pm1Mask) 0Xd144
Chapter 10 PCI Controller 10.4.36 G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0xD144 AM[35:20] : Type 0x0000 : Initial value AM[19:8] Reserved : Type 0x000 : Initial value Mnemonic Field Name Description Read/Write 31:4 AM[35:8] Address Mask G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) Sets the bits to be subject to address comparison.
Page 323: G2P Memory Space 2 Address Mask Register (G2Pm2Mask) 0Xd148
Chapter 10 PCI Controller 10.4.37 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0xD148 AM[35:20] : Type 0x0000/0x003F : Initial value AM[19:8] Reserved : Type 0x000/0xFFF : Initial value Mnemonic Field Name Description Read/Write 31:4 AM[35:8] Address Mask G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) (Default: Normal Mode: 0x0_0000_00;...
Page 324: G2P I/O Space Address Mask Register (G2Piomask) 0Xd14C
Chapter 10 PCI Controller 10.4.38 G2P I/O Space Address Mask Register (G2PIOMASK) 0xD14C AM[35:20] : Type 0x0000 : Initial value AM[19:8] Reserved : Type 0x000 : Initial value Bits Mnemonic Field Name Description Read/Write 31:4 AM[35:8] Address Mask G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) Sets the bits to be subject to address comparison.
Page 325: G2P Memory Space 0 Pci Base Address Register (G2Pm0Pbase) 0Xd150
Chapter 10 PCI Controller 10.4.39 G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0xD150 Reserved : Type : Initial value Reserved BA[39:32] : Type 0x00 : Initial value BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 0x00 : Initial value...
Page 326: G2P Memory Space 1 Pci Base Address Register (G2Pm1Pbase) 0Xd158
Chapter 10 PCI Controller 10.4.40 G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0xD158 Reserved : Type : Initial value Reserved BA[39:32] : Type 0x00 : Initial value BA[31:16] : Type 0x0000/0xBFC0 : Initial value BA[15:8] Reserved : Type 0x00 0x00 : Initial value...
Page 327: G2P Memory Space 2 Pci Base Address Register (G2Pm2Pbase) 0Xd160
Chapter 10 PCI Controller 10.4.41 G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0xD160 Reserved : Type : Initial value Reserved BA[39:32] : Type 0x00 : Initial value BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 0x00 : Initial value...
Page 328: G2P I/O Space Pci Base Address Register (G2Piopbase) 0Xd168
Chapter 10 PCI Controller 10.4.42 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0xD168 Reserved : Type : Initial value Reserved BA[39:32] : Type 0x00 : Initial value BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 0x00 : Initial value Bits...
Page 329: Pci Controller Configuration Register (Pciccfg) 0Xd170
Chapter 10 PCI Controller 10.4.43 PCI Controller Configuration Register (PCICCFG) 0xD170 Reserved GBWC : Type 0xfff : Initial value Reserved HRST SRST IRBER TCAR ICAEN LCFG Reserved G2PIOEN G2PM0EN G2PM1EN G2PM2EN : Type : Initial value Mnemonic Field Name Description Read/Write ⎯...
Page 330 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write SRST Software Reset Soft Reset (Default: 0x0) Performs PCI Controller software reset control. Data is also reloaded to the Configuration Space Register from EEPROM or from the Configuration Data Register. Please set this bit after the EEPROM Load End bit (PCICSTATUS.E2PDONE) is set.
Page 331 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write Target TCAR Target Configuration Access Ready (Default: 0x0/0x1) Configuration Specifies whether to accept PCI access as a target. Access Ready PCI controller receives a target access, when this bit is 1 and PCISTATUS.E2PDONE bit is 1.
Page 332: Pci Controller Status Register (Pcicstatus) 0Xd174
Chapter 10 PCI Controller 10.4.44 PCI Controller Status Register (PCICSTATUS) 0xD174 Reserved : Type : Initial value Reserved PERR SERR Reserved Reserved E2PDONE R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type ⎯ : Initial value Mnemonic Field Name Description Read/Write ⎯...
Page 333 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write ⎯ Reserved Initiator Write Initiator Write Busy (Busy: 0x0) Busy Indicates that a Write cycle was in progress when a Write cycle to the PCI Bus was executed. While a Write cycle is in progress, no error status to that Write cycle is reflected.
Page 334: Pci Controller Interrupt Mask Register (Pcicmask) 0Xd178
Chapter 10 PCI Controller 10.4.45 PCI Controller Interrupt Mask Register (PCICMASK) 0xD178 Reserved : Type : Initial value Reserved PMEIE TLBIE NIBIE ZIBIE GBEIE Reserved PERRIE SERRIE Reserved : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:11 Reserved PMEIE PME Detect...
Page 335: P2G Memory Space 0 G-Bus Base Address Register (P2Gm0Gbase) 0Xd180
Chapter 10 PCI Controller 10.4.46 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0xD180 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP P2GM0EN : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:29] Reserved : Type 0x00 : Initial value Reserved : Type : Initial value...
Page 336: P2G Memory Space 1 G-Bus Base Address Register (P2Gm1Gbase) 0Xd188
Chapter 10 PCI Controller 10.4.47 P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0xD188 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP P2GM1EN : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:24] Reserved : Type 0x00 : Initial value Reserved : Type : Initial value...
Page 337: P2G Memory Space 2 G-Bus Base Address Register (P2Gm2Gbase) 0Xd190
Chapter 10 PCI Controller 10.4.48 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0xD190 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP P2GM2EN : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:20] Reserved : Type 0x000 : Initial value Reserved : Type : Initial value...
Page 338: P2G I/O Space G-Bus Base Address Register (P2Giogbase) 0Xd198
Chapter 10 PCI Controller 10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198 Reserved : Type : Initial value Reserved EXFER BA[35:32] BSWAP P2GIOEN : Type : Initial value 0x0/0x1 0x1/0x0 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00...
Page 339: G2P Configuration Address Register(G2Pcfgadrs) 0Xd1A0
Chapter 10 PCI Controller 10.4.50 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0 The operation of any access to this register is undefined when the PCI Controller is in the Satellite mode. Reserved BUSNUM : Type 0x00 : Initial value DEVNUM FNNUM REGNUM TYPE : Type 0x00...
Page 340: G2P Configuration Data Register (G2Pcfgdata) 0Xd1A4
Chapter 10 PCI Controller 10.4.51 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4 This is the only register that supports Byte access and 16-bit Word access. The upper address bit of the PCI Configuration Space is specified by the G2P Configuration Address Register (G2PCFGADRS). The lower two bits of the address are specified by the lower two bits of the offset address in this register as shown in Figure 10.4.2.
Page 341: G2P Interrupt Acknowledge Data Register (G2Pintack) 0Xd1C8
Chapter 10 PCI Controller 10.4.52 G2P Interrupt Acknowledge Data Register (G2PINTACK) 0xD1C8 IIACKD : Type ⎯ : Initial value IIACKD : Type ⎯ : Initial value Bits Mnemonic Field Name Description Read/Write 31:0 IIACKD Initiator Interrupt Initiator Interrupt Acknowledge Address Port (Default--) Acknowledge An Interrupt Acknowledge cycle is generated on the PCI Bus when this Address Port...
Page 342: G2P Special Cycle Data Register (G2Pspc) 0Xd1Cc
Chapter 10 PCI Controller 10.4.53 G2P Special Cycle Data Register (G2PSPC) 0xD1CC ISCD : Type ⎯ : Initial value ISCD : Type ⎯ : Initial value Bits Mnemonic Field Name Description Read/Write 31:0 ISCD Initiator Special Initiator Special Cycle Data Port (Default--) Cycle Data Port When this register is written to, Special Cycles are generated on the PCI Bus depending on the data that is written.
Page 343: Configuration Data 0 Register (Pcicdata0) 0Xd1D0
Chapter 10 PCI Controller 10.4.54 Configuration Data 0 Register (PCICDATA0) 0xD1D0 : Type 0x0000 : Initial value : Type 0x0000 : Initial value Bits Mnemonic Field Name Description Read/Write 31:16 Device ID Device ID (Default: 0x0000) This is the data loaded in the Device ID Register of the PCI Configuration Space.
Page 344: Configuration Data 1 Register (Pcicdata1) 0Xd1D4
Chapter 10 PCI Controller 10.4.55 Configuration Data 1 Register (PCICDATA1) 0xD1D4 : Type 0x0000 : Initial value : Type 0x00 0x00 : Initial value Mnemonic Field Name Description Read/Write 31:8 Class Code Class Code (Default: 0x000000) This is the data loaded in the Class Code Register of the PCI Configuration Space.
Page 345: Configuration Data 2 Register (Pcicdata2) 0Xd1D8
Chapter 10 PCI Controller 10.4.56 Configuration Data 2 Register (PCICDATA2) 0xD1D8 SSID : Type 0x0000 : Initial value SSVID : Type 0x0000 : Initial value Bits Mnemonic Field Name Description Read/Write 31:16 SSID Sub System ID Subsystem ID (Default: 0x0000) This is the data loaded in the Sub System ID Register of the PCI Configuration space.
Page 346: Configuration Data 3 Register (Pcicdata3) 0Xd1Dc
Chapter 10 PCI Controller 10.4.57 Configuration Data 3 Register (PCICDATA3) 0xD1DC : Type 0x00 0x00 : Initial value : Type 0x00 0x00 : Initial value Bits Mnemonic Field Name Description Read/Write 31:24 Maximum Max_Lat (Maximum Latency) (Default: 0x00) Latency This is the data loaded in the Max_Lat Register of the PCI Configuration Space.
Page 347: Pdmac Chain Address Register (Pdmca) 0Xd200
Chapter 10 PCI Controller 10.4.58 PDMAC Chain Address Register (PDMCA) 0xD200 Reserved : Type : Initial value Reserved PDMCA[35:32] : Type undefined : Initial value PDMCA[31:16] : Type Undefined : Initial value PDMCA[15:3] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name...
Page 348: Pdmac G-Bus Address Register (Pdmga) 0Xd208
Chapter 10 PCI Controller 10.4.59 PDMAC G-Bus Address Register (PDMGA) 0xD208 Reserved : Type : Initial value Reserved PDMGA[35:32] : Type Undefined : Initial value PDMGA[31:16] : Type Undefined : Initial value PDMGA[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name...
Page 349: Pdmac Pci Bus Address Register (Pdmpa) 0Xd210
Chapter 10 PCI Controller 10.4.60 PDMAC PCI Bus Address Register (PDMPA) 0xD210 Reserved : Type : Initial value Reserved PDMPA[39:32] : Type Undefined : Initial value PDMPA[31:16] : Type Undefined : Initial value PDMPA[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name...
Page 350: Pdmac Count Register (Pdmctr) 0Xd218
Chapter 10 PCI Controller 10.4.61 PDMAC Count Register (PDMCTR) 0xD218 Reserved : Type : Initial value Reserved : Type : Initial value Reserved PDMCTR[23:16] : Type Undefined : Initial value PDMCTR[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name Description Read/Write...
Page 351: Pdmac Configuration Register (Pdmcfg) 0Xd220
Chapter 10 PCI Controller 10.4.62 PDMAC Configuration Register (PDMCFG) 0xD220 Reserved : Type : Initial value Reserved : Type : Initial value Reserved EXFER Reserved RSTFIFO : Type : Initial value Reserved REQDLY ERRIE XFRSIZE CHRST CHNEN BSWAP XFRACT Reserved NCCMPIE NTCMPIE XFRDIRC...
Page 352 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write Interrupt Enable on Transfer Done (Default: 0x0) Normal Data NTCMPIE 1: PDMAC generates an interrupt when the current data transfer is Transfer Complete complete. Interrupt Enable 0: PDMAC does not generate an interrupt when the current data transfer is complete.
Page 353: Pdmac Status Register (Pdmstatus) 0Xd228
Chapter 10 PCI Controller 10.4.63 PDMAC Status Register (PDMSTATUS) 0xD228 Reserved : Type : Initial value Reserved : Type : Initial value Reserved REQCNT FIFOCNT FIFOWP FIFORP : Type 0x00 : Initial value Reserved ERRINT CHNEN ACCMP NCCMP NTCMP PCIERR DONEINT XFRACT CFGERR...
Page 354 Chapter 10 PCI Controller Mnemonic Field Name Description Read/Write XFRACT Transfer Active Transfer Active (Default: 0x0) This bit is a copy of the Transfer Active bit in the PDMAC Configuration Register. Abnormal Chain ACCMP Abnormal Chain Complete (Default: 0x0) Completion 1: Indicates that the Chain transfer ended in an error state.
Page 355 Chapter 10 PCI Controller NCCMPIE NCCMP DONEINT Interrupt Controller NTCMPIE NTCMP (Interrupt No. 15) ERRIE STLTRF ERRINT CFGERR PCIERR ACCMP CHNERR DATAERR Figure 10.4.62 PDMAC Interrupt Signaling 10-97...
Page 356: Pci Configuration Space Register
Chapter 10 PCI Controller 10.5 PCI Configuration Space Register The PCI Configuration Space Register is accessed using PCI Configuration cycles by way of an external PCI host device only when in the Satellite mode. Table 10.5.1 lists registers contained within the PCI Configuration Space Register.
Page 357: Capability Id Register (Cap_Id) 0Xdc
Chapter 10 PCI Controller 10.5.1 Capability ID Register (Cap_ID) 0xDC Reserved : Type 0x01 : Initial value Bits Mnemonic Field Name Description Read/Write ⎯ 15:8 Reserved Capability ID Capability ID (Default: 0x01) Indicates that a list is the link list of the Power Management Register. Figure 10.5.1 Capability ID Register 10-99...
Page 358: Next Item Pointer Register (Next_Item_Ptr) 0Xdd
Chapter 10 PCI Controller 10.5.2 Next Item Pointer Register (Next_Item_Ptr) 0xDD Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description Read/Write ⎯ 15:8 Reserved Next Item Pointer (Default: 0x0) Next Item Pointer This is the Next Item pointer. Indicates the end of a list. Figure 10.5.2 Next Item Pointer Register 10-100...
Page 359: Power Management Capability Register (Pmc) 0Xde
Chapter 10 PCI Controller 10.5.3 Power Management Capability Register (PMC) 0xDE PMESPT D2SPT D1SPT Reserved PMVER Reserved PMECLK : Type 0x19 : Initial value Mnemonic Field Name Description Read/Write PME Output 15:11 PMESPT PME_ Support (Fixed Value: 0x09) Support Indicates that the PME* signal can be output from the state where the bit is set to “1”.
Page 360: Power Management Control/Status Register (Pmcsr) 0Xe0
Chapter 10 PCI Controller 10.5.4 Power Management Control/Status Register (PMCSR) 0xE0 Reserved Reserved PMEEN PMESTA R/W1C : Type : Initial value Mnemonic Field Name Description Read/Write PMESTA PME Status PME_Status (Default: 0x0) R/W1C Indicates the existence of a PME (Power Management Event) . 1: There is a PME.
Page 361: Serial I/O Port
Chapter 11 Serial I/O Port 11. Serial I/O Port 11.1 Features The TX4937 asynchronous Serial I/O (SIO) interface has two full duplex UART channels (SIO0 and SIO1). SIO has the following features. (1) Full duplex transmission (simultaneous transmission and reception) (2) On-chip baud rate generator (3) Modem flow control (CTS/RTS) (4) FIFO...
Page 362: Block Diagram
Chapter 11 Serial I/O Port 11.2 Block Diagram SCLK SIOCLK Baud Rate IMBUSCLK Baud Rate Control Register IM Bus Receiver RTS* Receive Data Receive Data Register FIFO Read Receiver Shift Buffer Register DMA/INT Control Register Interrupt I/F DMA/INT FIFO Control Status Register Register Read...
Page 363: Detailed Explanation
Chapter 11 Serial I/O Port 11.3 Detailed Explanation 11.3.1 Overview During reception, serial data that are input as an RXD signal from an external source are converted into parallel data, then are stored in the Receive FIFO buffer. Parallel data stored in the FIFO buffer are fetched by either CPU or DMA transfer.
Page 364 Chapter 11 Serial I/O Port 8-bit Data Transfer Direction stop bit2, parity Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity stop stop stop bit1, parity Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity stop stop bit2 Start bit0 bit1...
Page 365: Serial Clock Generator
Chapter 11 Serial I/O Port 11.3.3 Serial Clock Generator Generates the Serial Clock (SIOCLK). SIOCLK determines the serial transfer rate and has a frequency that is 16× the baud rate. One of the following can be selected as the source for the Serial Clock (SIOCLK).
Page 366 Chapter 11 Serial I/O Port Table 11.3.1 Example Divide Value Settings (and error [%] from target baud rate value) Prescalar Value (SIBGR.BLCK) and Divide Value (SIBGR.BRD) fc[MHz] kbps IMBUSCLK 0.11 0.15 215 -0.07% 0.30 0.39% 0.60 215 -0.07% 54 -0.54% 1.20 0.39% 27 -0.54%...
Page 367: Data Reception
Chapter 11 Serial I/O Port 11.3.4 Data Reception When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set to “0”, reception operation starts after the RXD signal start bit is detected. Start bits are detected when the RXD signal transitions from the High state to the Low state.
Page 368: Flow Control
Chapter 11 Serial I/O Port Transfer Size 1 Byte DMCCRn.XFSZ = 000b Transfer Address Mode Dual DMCCRn.SNGAD = 0 In the case of transmission channels, the address of the Transmit FIFO Register (SITFIFOn) is set in the DMAC Destination Address Register (DMDARn). In the case of reception channels, the address of the Receive FIFO Register (SIRFIFOn) is set in the DMAC Source Address Register (DMSARn).
Page 369: Reception Time Out
Chapter 11 Serial I/O Port The Reception Error Interrupt bit (SIDISR.ERI) of the DMA/Interrupt Status Register (SIDISRn) is set when one of the following errors is detected: an overrun error, a parity error, or a framing error. An interrupt is signaled if the Reception Error Interrupt Enable bit of the DMA/Interrupt Control Register (SIDICRn) is set.
Page 370: Error Detection/Interrupt Signaling
Chapter 11 Serial I/O Port 11.3.11 Error Detection/Interrupt Signaling An interrupt is signaled if an error or an interrupt cause is detected, the corresponding status bit is set and the corresponding Interrupt Enable bit is set. The following figure shows the relationship between the status bit for each interrupt cause and each interrupt enable bit.
Page 371: Multi-Controller System
Chapter 11 Serial I/O Port 11.3.12 Multi-Controller System The Multi-Controller System consists of one Master Controller, and multiple Slave Controllers as shown below in Figure 11.3.4. In the case of the Multi-Controller System, the Master Controller transmits an address (ID) frame to all Slave Controllers, then transmits and receives data with the selected Slave Controller.
Page 372: Registers
Chapter 11 Serial I/O Port 11.4 Registers With the exception of DMA access to the Transmit FIFO Register or the Receive FIFO Register, please use Word access when accessing register in the Serial I/O Port. Table 11.4.1 SIO Registers Offset Address Mnemonic Register Name SIO0 (Channel 0)
Page 373: Line Control Register 0 (Silcr0) 0Xf300 (Ch. 0) Line Control Register 1 (Silcr1) 0Xf400 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.1 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0) Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) These registers specify the format of asynchronous transmission/reception data. Reserved : Type : Initial value R/WUB TWUB UODE Reserved UEPS UPEN USBL UMODE...
Page 374 Chapter 11 Serial I/O Port Mnemonic Field Name Description Read/Write USBL Stop Bit Length UART Stop Bit Length (Default: 0) This field specifies the stop bit length. 0: 1 bit 1: 2 bit UMODE Mode UART Mode (Default: 00) This field sets the data frame mode. 00: 8-bit data length 01: 7-bit data length 10: Multi-Controller 8-bit data length...
Page 375: Dma/Interrupt Control Register 0 (Sidicr0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (Sidicr1) 0Xf404 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0) DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1) These registers use either DMA or interrupts to execute the Host Interface. Reserved : Type : Initial value SPIE CTSAC Reserved...
Page 376 Chapter 11 Serial I/O Port Mnemonic Field Name Description Read/Write Status Change STIE Status Change Interrupt Enable (Default: 0x00) Interrupt Enable This field sets the set conditions of the Status Change bit (STIS) of the DMA/Interrupt Status Register (SIDISR). The condition is selected depending on which bit of the Status Change Interrupt Status Register (SISCISR) is set.
Page 377: Dma/Interrupt Status Register 0 (Sidisr0) 0Xf308 (Ch. 0) Dma/Interrupt Status Register 1 (Sidisr1) 0Xf408 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.3 DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0) DMA/Interrupt Status Register 1 (SIDISR1) 0xF408 (Ch. 1) These registers indicate the DMA or interrupt status information. Reserved : Type : Initial value UBRK UFER UPER UOER TOUT TDIS RDIS STIS...
Page 378 Chapter 11 Serial I/O Port Mnemonic Field Name Description Read/Write RDIS Reception Data Receive DMA/Interrupt Status (Default: 0) R/W0C Full This bit is set when valid data of the amount set by the Receive FIFO Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored in the Receive FIFO.
Page 379: Status Change Interrupt Status Register 0 (Siscisr0) 0Xf30C (Ch. 0) Status Change Interrupt Status Register 1 (Siscisr1) 0Xf40C (Ch. 1)
Chapter 11 Serial I/O Port 11.4.4 Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0) Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1) Reserved : Type : Initial value Reserved OERS CTSS TRDY TXALS RBRKD UBRKD R/W0C R/W0C : Type : Initial value Mnemonic...
Page 380: Fifo Control Register 0 (Sifcr0) 0Xf310 (Ch. 0) Fifo Control Register 1 (Sifcr1) 0Xf410 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.5 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1) These registers set control of the Transmit/Receive FIFO buffer. Reserved : Type : Initial value Reserved RDIL Reserved TDIL SWRST TFRST RFRST FRSTE...
Page 381: Flow Control Register 0 (Siflcr0) 0Xf314 (Ch. 0) Flow Control Register 1 (Siflcr1) 0Xf414 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.6 Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0xF414 (Ch. 1) Reserved : Type : Initial value Reserved RSDE TSDE Reserved RTSTL TBRK RTSSC Reserved R/W : Type 0001 : Initial value Mnemonic Field Name...
Page 382: Baud Rate Control Register 0 (Sibgr0) 0Xf318 (Ch. 0) Baud Rate Control Register 1 (Sibgr1) 0Xf418 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.7 Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch. 0) Baud Rate Control Register 1 (SIBGR1) 0xF418 (Ch. 1) These registers select the clock that is provided to the baud rate generator and set the divide value. Reserved : Type : Initial value...
Page 383: Transmit Fifo Register 0 (Sitfifo0) 0Xf31C (Ch. 0) Transmit Fifo Register 1 (Sitfifo1) 0Xf41C (Ch. 1)
Chapter 11 Serial I/O Port 11.4.8 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller.
Page 384: Receive Fifo Register 0 (Sirfifo0) 0Xf320 (Ch. 0) Receive Fifo Register 1 (Sirfifo1) 0Xf420 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller.
Page 385: Timer/Counter
Chapter 12 Timer/Counter 12. Timer/Counter 12.1 Features The TX4937 has an on-chip 3-channel timer/counter. • 32-bit Up Counter: 3 Channels • Interval Timer Mode (Channel 0, 1, 2) • Pulse Generator Mode (Channel 0, 1) • Watchdog Timer Mode (Channel 2) •...
Page 386: Block Diagram
Chapter 12 Timer/Counter 12.2 Block Diagram TX4937 IM-Bus I/F Signal TIMER[0] Timer-0 Counter Input Clock Interval Timer Mode Timer Interrupt 0 Timer-1 IM-Bus I/F Signal TIMER[1] Pulse Generator Mode Counter Input Clock Interval Timer Mode Timer Interrupt 1 IM-Bus I/F Signal Timer-2 Counter Input Clock Interval Timer Mode...
Page 387: Detailed Explanation
Chapter 12 Timer/Counter 12.3 Detailed Explanation 12.3.1 Overview The TX4937 has an on-chip 3-channel 32-bit timer/counter. Each channel supports the following modes. (1) Interval Timer Mode (Timer 0, 1, 2) This mode periodically generates interrupts. (2) Pulse Generator Mode (Timer 0, 1) This is the pulse signal output mode.
Page 388: Counter
Chapter 12 Timer/Counter Table 12.3.2 Divide Value and Count (IMBUSCLK = 66 MHz) Divide TMCCDRn. Counter Clock Max. Set Time TMCPRAn Value Resolution (ns) Rate Frequency (Hz) (sec.) for 1 sec. 33.0 M 30.30 130.15 33000000 16.5 M 60.61 260.30 16500000 8.3 M 121.21...
Page 389 Chapter 12 Timer/Counter Count Value TMCPRA Reg. Compare Value 0x000000 Time TCE = 1 TCE = 0 TCE = 1 TCE = 0 TCE = 1 TCE = 0 CRE = 1 CRE = 0 CRE = 0 TZCE = 1 TZCE = 0 TZCE = 1 TIIE = 1 TIIE = 0 TIIE = 1...
Page 390: Pulse Generator Mode
Chapter 12 Timer/Counter 12.3.5 Pulse Generator Mode When in the Pulse Generator mode, use Compare Register A (TMCPRAn) and Compare Register B (TMCPRBn) to output a particular period and particular duty square wave to the TIMER[n] signal. Setting the Timer Mode field (TMTCRn.TMODE) of the Timer Control Register to “01” sets the timer to the Pulse Generator mode.
Page 391: Watchdog Timer Mode
Chapter 12 Timer/Counter 12.3.6 Watchdog Timer Mode The Watchdog Timer mode is used to monitor system anomalies. The software periodically clears the counter and judges an anomaly to exist if the counter is not cleared within a specified period of time. Then, either the TX4937 is internally reset or an NMI is signaled to the TX49/H3 core.
Page 392 Chapter 12 Timer/Counter In Watchdog Timer mode, the TIMER[1:0] outputs remain at logic high. Count Value TMCPRA2 Compare Value 0x000000 Time TCE = 1 TCE = 0 TCE = 1 TWC = 1 TWC = 1 TWC = 1 TWIE = 0 TWIE = 0 TWIE = 1 TWIE = 1 TWIS = 1...
Page 393: Registers
Chapter 12 Timer/Counter 12.4 Registers Table 12.4.1 Timer Register List Offset Address Register Symbol Register Name Time 0 (TMR0) 0xF000 TMTCR0 Timer Control Register 0 0xF004 TMTISR0 Timer Interrupt Status Register 0 0xF008 TMCPRA0 Compare Register A 0 0xF00C TMCPRB0 Compare Register B 0 0xF010 TMITMR0...
Page 394 Chapter 12 Timer/Counter 12.4.1 Timer Control Register n (TMTCRn) TMTCR0 0xF000 TMTCR1 0xF100 TMTCR2 0xF200 Reserved : Type : Initial value Reserved CCDE ECES TMODE Reserved : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:8 Reserved Timer Counter Timer Count Enable (Default: 0) Enable This field controls whether the counter runs or stops.
Page 395: Timer Interrupt Status Register N (Tmtisrn) Tmtisr0 0Xf004 Tmtisr1 0Xf104 Tmtisr2 0Xf204
Chapter 12 Timer/Counter 12.4.2 Timer Interrupt Status Register n (TMTISRn) TMTISR0 0xF004 TMTISR1 0xF104 TMTISR2 0xF204 Reserved : Type : Initial value Reserved TWIS TPIBS TPIAS TIIS RW0C RW0C RW0C RW0C : Type : Initial value Mnemonic Field Name Description Read/Write ⎯...
Page 396: Tmcpra2 0Xf208
Chapter 12 Timer/Counter 12.4.3 Compare Register An (TMCPRAn) TMCPRA0 0xF008 TMCPRA1 0xF108 TMCPRA2 0xF208 TCVA : Type 0xFFFF : Initial value TCVA : Type : Initial value 0xFFFF Bits Mnemonic Field Name Description Read/Write 31:0 TCVA Timer Compare Timer Compare Value A (Default: 0xFFFFFFFF) Register A Sets the timer compare value as a 32-bit value.
Page 397: Compare Register Bn (Tmcprbn) Tmcprb0 0Xf00C Tmcprb1 0Xf10C
Chapter 12 Timer/Counter 12.4.4 Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C TMCPRB1 0xF10C TCVB : Type 0xFFFF : Initial value TCVB : Type : Initial value 0xFFFF Bits Mnemonic Field Name Description Read/Write 31:0 TCVB Timer Compare Timer Compare Value B (Default: 0xFFFFFFFF) Value B Sets the timer compare value as a 32-bit value.
Page 398: Tmitmr2 0Xf210
Chapter 12 Timer/Counter 12.4.5 Interval Timer Mode Register n (TMITMRn) TMITMR0 0xF010 TMITMR1 0xF110 TMITMR2 0xF210 Reserved : Type : Initial value TIIE Reserved TZCE R/W : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:16 Reserved TIIE Interval Timer Timer Interval Interrupt Enable (Default: 0) Interrupt Enable...
Page 399 Chapter 12 Timer/Counter 12.4.6 Divide Register n (TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 Reserved : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description Read/Write ⎯ 31:3 Reserved Counter Clock Counter Clock Divide (Default: 000) Divide Value These bits specify the divide value when using the internal clock (IMBUSCLK) as the counter input clock source.
Page 400: Pulse Generator Mode Register N (Tmpgmrn) Tmpgmr0 0Xf000 Tmpgmr1 0Xf130
Chapter 12 Timer/Counter 12.4.7 Pulse Generator Mode Register n (TMPGMRn) TMPGMR0 0xF000 TMPGMR1 0xF130 Reserved : Type : Initial value TPIBE TPIAE Reserved R/W : Type : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:16 Reserved TPIBE TMCPRB Timer Pulse Generator Interrupt by TMCPRB Enable (Default: 0) Interrupt Enable When in the Pulse Generator mode, this bit sets Interrupt Enable/Disable for when TMCPRB and the counter value match.
Page 401: Watchdog Timer Mode Register N (Tmwtmrn) Tmwtmr2 0Xf240
Chapter 12 Timer/Counter 12.4.8 Watchdog Timer Mode Register n (TMWTMRn) TMWTMR2 0xF240 Reserved : Type : Initial value TWIE Reserved WDIS R/W1C : Type RW1S : Initial value Mnemonic Field Name Description Read/Write ⎯ 31:16 Reserved TWIE Watchdog Timer Timer Watchdog Enable (Default: 0) Signaling Enable This bit sets NMI signaling enable/disable either when in the Watchdog Timer mode or during a reset.
Page 402: Tmtrr2 0Xf2F0
Chapter 12 Timer/Counter 12.4.9 Timer Read Register n (TMTRRn) 0xF0F0 TMTRR0 0xF0F0 TMTRR1 0xF1F0 TMTRR2 0xF2F0 TCNT : Type 0x0000 : Initial value TCNT : Type : Initial value 0x0000 Bits Mnemonic Field Name Description Read/Write 31:0 TCNT Timer Counter Timer Counter (Default: 0x00000000) This Read Only register is a 32-bit counter.
Page 403: Parallel I/O Port
Chapter 13 Parallel I/O Port 13. Parallel I/O Port 13.1 Characteristics The TX4937 on-chip Parallel I/O port (PIO) is a 16-bit general-purpose parallel port. The input/output direction and the port type during output (totem pole output/open drain output) can be set for each bit. 13.2 Block Diagram CB[7:0]/PIO[15:8] SDRAMC...
Page 404: Detailed Description
Chapter 13 Parallel I/O Port 13.3 Detailed Description 13.3.1 Selecting PIO Pins Of the 16-bit PIO signals, signals PIO[15:8] can be used in combination with 8-bit ECC check bit signals. The configuration signal (ADDR[18]) at boot up determines which function will be used. See 3.3 Configuration Signals for more information.
Page 405: Pio Output Data Register (Piodo) 0Xf500
Chapter 13 Parallel I/O Port 13.4.1 PIO Output Data Register (PIODO) 0xF500 Reserved :Type :Initial value :Type 0x0000 :Initial value Mnemonic Field Name Description Read/Write ⎯ 31:16 Reserved 15 :0 PDO [15:0] Data Out Port Data Output [15:0] (Initial value:0x0000) Data that is output to the PIO pin (PIO [15:0]).
Page 406: Pio Direction Control Register (Piodir) 0Xf508
Chapter 13 Parallel I/O Port 13.4.3 PIO Direction Control Register (PIODIR) 0xF508 Reserved :Type :Initial value PDIR :Type 0x0000 :Initial value Mnemonic Field Name Description Read/Write ⎯ 31:16 Reserved 15 :0 PDIR [15:0] Direction Control Port Direction Control [15:0] (Initial value: 0x0000) Sets the I/O direction of the PIO pin (PIO [15:0]).
Page 407: Ac-Link Controller
Chapter 14 AC-link Controller 14. AC-link Controller 14.1 Features ACLC, AC-link controller module can be connected to audio and/or modem CODECs described in the “Audio CODEC ’97 Revision 2.1” (AC’97) defined by Intel and can operate them. Refer to the following Web site for more information regarding the AC’97 specification.
Page 408: Configuration
Chapter 14 AC-link Controller 14.2 Configuration Figure 14.2.1 illustrates the ACLC configuration. DMAC IM-bus aclcimbif Bus I/F System-side aclc (imclk / imreset* ) Data I/O Master Slave Register Wakeup Control Asynchronous Handshake Slot-data Slot Valid/Req & Transfer Register Access Link-side (BITCLK / ACRESET* ) Bitstream Receive &...
Page 409: Functional Description
Chapter 14 AC-link Controller 14.3 Functional Description ACLC provides four mechanisms to operate AC’97-compliant CODEC(s): • AC-link status control (start-up and low-power mode) • CODEC register access • Sample-data transmission and reception • GPIO operation This section first describes the CODEC connection, chip configuration, and overall usage-flow. Then AC- link start-up sequence and the other mechanisms will be described.
Page 410: Boot Configuration
Chapter 14 AC-link Controller 14.3.1.2 5.1 Channel Audio Connection This sample assumes one CODEC with four DACs mapped to stereo front (3&4) and stereo rear (7&8) slots, and another CODEC with two DACs mapped to center (6) and LFE (9) slots. ACLC 4Channel Audio CODEC (CODEC ID=’0’) SYNC...
Page 411: Usage Flow
Chapter 14 AC-link Controller 14.3.3 Usage Flow This section outlines a process flow when using the AC’97 connected to ACLC. Refer to the subsequent sections for the details of each operation performed in this process flow. The diagrams below describe the audio playback and recording processes. The modem transmission and reception can be done in a similar way.
Page 412 Chapter 14 AC-link Controller System Software ACLC and DMAC AC’97 Enable ENLINK Deassert ACRESET* Start BITCLK Set CODEC Ready CODECRDY Interrupt Check AC’97 status Start recording audio ADC Ready response Start up AC-link Register setting such as gain (*) Set gain, etc. Clear DMA buffer Configure DMAC Start DMA Channel and...
Page 413: Ac-Link Start Up
Chapter 14 AC-link Controller 14.3.4 AC-link Start Up Figure 14.3.5 shows the conceptual sequence of AC-link start-up. The ACLC Control Enable Register’s Enable AC-link bit is used to deassert/assert the ACRESET* signal to the link side (including AC-link). This bit defaults to ‘0’, so the CPU asserts the ACRESET* signal when it boots up.
Page 414: Codec Register Access
Chapter 14 AC-link Controller 14.3.5 CODEC Register Access By accessing registers in the CODEC, the system software is able to detect or control the CODEC state. This section describes how to read and write CODEC registers via ACLC. For details about AC’97 register set and proper sequence to operate CODEC, refer to the AC’97 specification and target CODEC datasheet.
Page 415: Sample-Data Transmission And Reception
Chapter 14 AC-link Controller 14.3.6 Sample-data Transmission and Reception This section describes the mechanism for transmission and reception of PCM audio and modem wave-data. An overview is described first. The DMA (Direct Memory Access) operation, error detection and recovery procedure follow. A special case using slot activation control is described last. 14.3.6.1 Overview Figure 14.3.6 and Figure 14.3.7 show conceptual views of the sample-data transmission and reception mechanisms.
Page 416 Chapter 14 AC-link Controller 14.3.6.2 DMA Channel Mapping ACLC uses four DMA request channels. These DMA channels are allocated to four out of seven data-streams, or slots, on the AC-link frame, according to ACLC DMA Channel Selection Register (ACDMASEL) setting as shown in Table 14.3.1. The pin configuration register allocates these DMA channels of ACLC to the DMAC (DMA controller) channels according to Pin Configuration Register (PCFG)’s DMA Request Selection (DMASEL[7:0]) bits as described in section 8.3.1.
Page 417 Chapter 14 AC-link Controller Figures below show the format of DMA buffer for each type of DMA channel. #0, #1, … means the sample’s sequential number for the AC-link slot. Subscript ‘L’ means lower 8-bit of each sample and subscript ‘ ’...
Page 418 Chapter 14 AC-link Controller 14.3.6.4 DMA Operation When ACLC’s REQ latch (refer to Figure 14.3.6 and Figure 14.3.7) needs to read or write sample-data, it issues a DMA request. When DMAC acknowledges the request by performing write- or read-access to the ACLC sample-data register, ACLC deasserts the request. Therefore, the software must properly set up DMAC so that the source or destination points to the corresponding sample-data register for the DMA channel.
Page 419 Chapter 14 AC-link Controller 14.3.6.5 Sample-data FIFO For a transmission stream, as long as ACLC Control Enable Register (ACCTLEN) allows that transmission and the FIFO has any room to fill data in, the FIFO issues a request via the REQ latch.
Page 420: Gpio Operation
Chapter 14 AC-link Controller 14.3.6.7 Slot Activation Control In case ACLC is required to begin transmission or reception of multiple streams at the same time, slot activation control will be useful. To use this feature, the software must deactivate the relevant streams first, enable ACLC Control Enable Register (ACCTLEN), make sure the transmission FIFO becomes full by checking ACLC FIFO Status Register (ACFIFOSTS)’s Full (xxxxFULL) bit, and finally enable ACLC Slot Enable Register (ACSLTEN).
Page 421: Interrupt
Chapter 14 AC-link Controller 14.3.8 Interrupt ACLC generate two kinds of interrupt to the interrupt controller as below. • ACLC Interrupt Logical OR of all the valid bits of ACLC Interrupt Masked Status Register (ACINTMSTS) is connected. Refer to the section 14.4.5. •...
Page 422: Registers
Chapter 14 AC-link Controller 14.4 Registers The base address for the ACLC registers is described in section 4.2. Only word (32-bit) accesses are allowed. These registers return to their initial values when the module gets reset by power-on or configuration-register operation. The ‘Disable AC-link’ operation initializes the ACREGACC, ACGPIDAT, ACGPODAT, and ACSLTEN registers while keeping the other registers.
Page 423: Aclc Control Enable Register 0Xf700
Chapter 14 AC-link Controller 14.4.1 ACLC Control Enable Register 0xF700 This register is used to check the setting of various ACLC features and to enable them. MODIE MODOE AUDIE LFEEH CENTE SURRE AUDO Reserved Reserved EHLT : Type R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S : Initial value MODID...
Page 424 Chapter 14 AC-link Controller Mnemonic Field Name Description Read/Write Enable Audio SURREHLT SURREHLT: Enable Audio Surround L&R Transmit-data DMA Error Halt. R/W1S Surround L&R 0: Indicates that SURRDMA error halt is disabled. Transmit-data 1: Indicates that SURRDMA error halt is enabled. DMA Error Halt 0: No effect 1: Enables SURRDMA error halt.
Page 425 Chapter 14 AC-link Controller Mnemonic Field Name Description Read/Write ⎯ ⎯ Reserved Clear CODEC RDYCLR RDYCLR: Clear CODEC Ready Bit Ready Bit 0: No effect 1: Clear CODEC[1:0] ready bits [Note: This bit should only be written to reevaluate the CODEC ready status after power-down command is sent to CODEC.] MIC Selection MICSEL: MIC Selection.
Page 426: Aclc Control Disable Register 0Xf704
Chapter 14 AC-link Controller 14.4.2 ACLC Control Disable Register 0xF704 This register is used to disable various ACLC features. MODIE MODO AUDIE LFEEH CENTE SURRE AUDO Reserved EHLT EHLT Reserved W1C : Type : Initial value MODID MODO AUDID LFED CENTD SURR AUDO...
Page 427 Chapter 14 AC-link Controller Mnemonic Field Name Description Read/Write ⎯ Reserved — AUDIDMA: Disable Audio Receive-data DMA. 0: No effect 1: Disables audio receive-data DMA. — LFEDMA: Disable Audio LFE Transmit-data DMA. 0: No effect 1: Disables audio LFE transmit-data DMA. —...
Page 428: Aclc Codec Register Access Register 0Xf708
Chapter 14 AC-link Controller 14.4.3 ACLC CODEC Register Access Register 0xF708 CODEC registers can be accessed through this register. CODE Reserved CODECID REGADR Reserved : Type : Initial value REGDAT : Type : Initial value Mnemonic Field Name Description Read/Write CODECRD AC’97 register CODECRD: AC’97 register read access...
Page 429: Aclc Interrupt Status Register 0Xf710
Chapter 14 AC-link Controller 14.4.4 ACLC Interrupt Status Register 0xF710 This register shows various kinds of AC-link and ACLC status. Reserved : Type : Initial value MODIE MODOE AUDIE CENTE SURRE AUDOE REGAC CODEC CODEC Reserved Reserved Reserved LFEERR GPIOINT CRDY 1RDY 0RDY...
Page 430 Chapter 14 AC-link Controller Mnemonic Field Name Description Read/Write REGACCRDY ACREGACC REGACCRDY: ACREGACC Ready R/W1C Ready 1: Indicates that the ACREGACC register is ready to get the value (in case the previous operation was a read access) and to initiate another R/W access to an AC’97 register. The result of reading or writing to the ACREGACC register before the completion notification is undefined.
Page 431: Aclc Interrupt Masked Status Register 0Xf714
Chapter 14 AC-link Controller 14.4.5 ACLC Interrupt Masked Status Register 0xF714 Every bit in this register is configured as follows: ACINTMSTS = ACINTSTS & ACINTEN Bit placement is the same as for the ACINTSTS register. The logical OR of all bits in this register is used as ACLC interrupt request to the interrupt controller.
Page 432: Aclc Semaphore Register 0Xf720
Chapter 14 AC-link Controller 14.4.8 ACLC Semaphore Register 0xF720 This register is used for mutual exclusion control for resource. SEMAPH RS/WC : Type : Initial value SEMAPH RS/WC : Type : Initial value Mnemonic Field Name Description Read/Write 31:0 SEMAPH Semaphore flag SEMAPH: Semaphore flag.
Page 433: Aclc Gpi Data Register 0Xf740
Chapter 14 AC-link Controller 14.4.9 ACLC GPI Data Register 0xF740 This register shows GPIO (slot 12) input data. Reserved GPIDAT : Type 0x00000 : Initial value GPIO GPIDAT : Type 0x00000 : Initial value Mnemonic Field Name Description Read/Write ⎯ ⎯...
Page 434: Aclc Gpo Data Register 0Xf744
Chapter 14 AC-link Controller 14.4.10 ACLC GPO Data Register 0xF744 This register specifies GPIO (slot 12) output data. Reserved GPODAT WRPEND : Type 0x00000 : Initial value GPODAT : Type 0x00000 : Initial value Mnemonic Field Name Description Read/Write ⎯ ⎯...
Page 435: Aclc Slot Enable Register 0Xf748
Chapter 14 AC-link Controller 14.4.11 ACLC Slot Enable Register 0xF748 This register enables independently the AC-link slot data streams. Reserved WRPEND : Type : Initial value MODO CENT SURR AUDO Reserved GPISLT GPOSLT MODISLT Reserved AUDISLT LFESLT R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S : Type : Initial value...
Page 436 Chapter 14 AC-link Controller Mnemonic Field Name Description Read/Write Enable Audio AUDISLT AUDISLT: Enable Audio slot reception. R/W1S slot reception 0: Indicates that audio slot reception is disabled. 1: Indicates that audio slot reception is enabled. 0: No effect 1: Enables audio slot reception. LFESLT Enable Audio LFESLT: Enable Audio LFE slot transmission.
Page 437: Aclc Slot Disable Register 0Xf74C
Chapter 14 AC-link Controller 14.4.12 ACLC Slot Disable Register 0xF74C This register disables independently the AC-link slot data streams. Reserved : Type : Initial value MODI MODO AUDI CENT SURR AUDO Reserved GPISLT GPOSLT Reserved LFESLT W1C : Type : Initial value Mnemonic Field Name Description...
Page 438: Aclc Fifo Status Register 0Xf750
Chapter 14 AC-link Controller 14.4.13 ACLC FIFO Status Register 0xF750 This register indicates the AC-link slot data FIFO status. Reserved : Type : Initial value MODO CENT SURR AUDO MODI MODO AUDI CENT SURR AUDO Reserved Reserved Reserved LFEFILL FULL FULL FULL FULL...
Page 439 Chapter 14 AC-link Controller Mnemonic Field Name Description Read/Write Audio Center CENTFILL CENTFILL: Audio Center Transmit-data Filled. Transmit-data 0: Indicates audio Center transmit-data FIFO is empty. Filled 1: Indicates audio Center transmit-data FIFO is not empty. SURRFILL Audio Surround SURRFILL: Audio Surround L&R Transmit-data Filled. L&R 0: Indicates audio Surround L&R transmit-data FIFO is empty.
Page 440 Chapter 14 AC-link Controller 14.4.14 ACLC DMA Request Status Register 0xF780 This register indicates the AC-link slot data DMA request status. Reserved : Type : Initial value MODI MODO AUDI CENT SURR AUDO Reserved Reserved LFEREQ : Type : Initial value Mnemonic Field Name Description...
Page 441: Aclc Dma Channel Selection Register 0Xf784
Chapter 14 AC-link Controller 14.4.15 ACLC DMA Channel Selection Register 0xF784 This register is used to select and check the channel allocation for AC-link slot data DMA. Reserved : Type : Initial value Reserved ACDMASEL : Type : Initial value Mnemonic Field Name Description...
Page 442: Aclc Audio Pcm Output Data Register 0Xf7A0
Chapter 14 AC-link Controller 14.4.16 ACLC Audio PCM Output Data Register 0xF7A0 ACLC Surround Data Register 0xF7A4 These registers are used to write audio PCM and surround L&R output data. DAT1: Sample Right (Little-endian mode) / DAT0: Sample Left (Big-endian mode) : Type : Initial value DAT0: Sample Left (Little-endian mode) / DAT1: Sample Right (Big-endian mode)
Page 443: Aclc Center Data Register 0Xf7A8
Chapter 14 AC-link Controller 14.4.17 ACLC Center Data Register 0xF7A8 ACLC LFE Data Register 0xF7AC ACLC Modem Output Data Register 0xF7B8 This registers are used to write audio center, LFE, and modem output data. DAT1: Sample data 1 (Little-endian mode) / DAT0: Sample data 0 (Big-endian mode) : Type : Initial value DAT0: Sample data 0 (Little-endian mode) / DAT1: Sample data 1 (Big-endian mode)
Page 444: Aclc Audio Pcm Input Data Register 0Xf7B0
Chapter 14 AC-link Controller 14.4.18 ACLC Audio PCM Input Data Register 0xF7B0 This register is used to read audio PCM input data. DAT1: Sample Right or ‘0’ (Little-endian mode) / DAT0: Sample Left or MIC (Big-endian mode) : Type : Initial value Undefined DAT0: Sample Left or MIC (Little-endian mode) / DAT1: Sample Right or ‘0’...
Page 445: Aclc Modem Input Data Register 0Xf7Bc
Chapter 14 AC-link Controller 14.4.19 ACLC Modem Input Data Register 0xF7BC This register is used to read modem input data. DAT1: Sample data 1 (Little-endian mode) / DAT0: Sample data 0 (Big-endian mode) : Type : Initial value Undefined DAT0: Sample data 0 (Little-endian mode) / DAT1: Sample data 1 (Big-endian mode) : Type : Initial value Undefined...
Page 446: Aclc Revision Id Register 0Xf7Fc
⎯ ⎯ 31:16 Reserved ⎯ ⎯ 15:8 Major Revision Contact Toshiba technical staff for an explanation of the revision value. ⎯ ⎯ Minor Revision Contact Toshiba technical staff for an explanation of the revision value. Figure 14.4.17 ACREVID Register This read-only register shows the revision of ACLC module. Note that this number is not related to the AC’97 specification revision.
Page 447: Interrupt Controller
Chapter 15 Interrupt Controller 15. Interrupt Controller 15.1 Characteristics The TX4937 on-chip Interrupt Controller (IRC) receives interrupt requests from the TX4937 on-chip peripheral circuitry as well as external interrupt requests then generates interrupt requests to the TX49/H3 processor core. Also, the Interrupt Controller has a 16-bit flag register that generates interrupt requests to either external devices or to the TX49/H3 core.
Page 448: Block Diagram
Chapter 15 Interrupt Controller 15.2 Block Diagram External Interrupt Signal (INT[5:0]) TX49/H3 Core Interrupt Controller Internal Timer ECC Error Interrupt Request TX49 Write time out Error SIO[1:0] Interrupt Detection Circuit DMA0[3:0] Request DMA1[3:0] (IP[7:2]) [7:2] Set Interrupt Level TMR[2:0] [6:2] ACLC PDMAC0 Internal...
Page 449 Chapter 15 Interrupt Controller Interrupt Detection Interrupt Level Interrupt Mask Interrupt Detection Mode IRDM0-1 IRLVL0-7 Level IRMSK Detection Circuit Level Interrupt Source High Level Interrupt Encoder IP [2] Negative Prioritization Interrupt Edge Edge IRCS.FL Detector Interrupt Positive Pending Edge IRPND Edge IP [7:3] Detector...
Page 450: Detailed Explanation
Chapter 15 Interrupt Controller 15.3 Detailed Explanation 15.3.1 Interrupt sources The TX4937 has as interrupt sources interrupts from 18 types of on-chip peripheral circuits and 6 external interrupt signals. Table 15.3.1 lists the interrupt sources. Signals with the lower interrupt number have the higher priority.
Page 451: Interrupt Request Detection
Chapter 15 Interrupt Controller In addition to the above, the TX49/H3 core has a TX49/H3 core internal timer interrupt and two software interrupts, but these interrupts are directly reported to the TX49/H3 core independently of this Interrupt Controller. Please refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture”...
Page 452: Interrupt Priority Assigning
Chapter 15 Interrupt Controller 15.3.4 Interrupt priority assigning When multiple interrupt requests exist, the Interrupt Controller selects the interrupt with the highest priority according to the priority level and interrupt number. Interrupt factors with an interrupt level equal to or lower than the interrupt level specified by the Interrupt Mask Level Register (IRMSK) will be excluded (masked).
Page 453: Interrupt Notification
Chapter 15 Interrupt Controller 15.3.5 Interrupt notification When the interrupt with the highest priority is selected, then the interrupt factor is reported to the Interrupt Current Status Register (IRCS) and an interrupt is reported to the TX49/H3 core. The TX49/H3 core distinguishes interrupt factors using the IP field (IP[7:2]) of the Cause Register. The interrupt notification from the Interrupt Controller is reflected in the IP[2] bit.
Page 454: Interrupt Requests
Chapter 15 Interrupt Controller 15.3.7 Interrupt requests It is possible to make interrupt requests to external devices and interrupt requests (IRC interrupts) to the TX49/H3 core by using a 16-bit interrupt request flag register. REQ[1]* signals are used as interrupt output signals.
Page 455 Chapter 15 Interrupt Controller There are two flag registers: Flag Register 0 (IRFLAG0), and Flag Register 1 (IRFLAG1). These registers have two different Write methods. Accordingly, Writes to one register are reflects in the other. Either “0” or “1” can be written to Flag Register 0 In the case of Flag Register 1 however, “1”...
Page 456: Registers
Chapter 15 Interrupt Controller 15.4 Registers Table 15.4.1 Interrupt Control Registers Address Register Register Name 0xF600 IRDEN Interrupt Detection Enable Register 0xF604 IRDM0 Interrupt Detection Mode Register 0 0xF608 IRDM1 Interrupt Detection Mode Register 1 0xF610 IRLVL0 Interrupt Level Register 0 0xF614 IRLVL1 Interrupt Level Register 1...
Page 457: Interrupt Detection Enable Register (Irden) 0Xf600
Chapter 15 Interrupt Controller 15.4.1 Interrupt Detection Enable Register (IRDEN) 0xF600 Reserved : Type : Default Reserved R/W : Type : Default Bit(s) Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:1 Reserved Interrupt Control Interrupt Detection Enable (Default: 0) Enable Enables interrupt detection.
Page 458: Interrupt Detection Mode Register 0 (Irdm0) 0Xf604
Chapter 15 Interrupt Controller 15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604 IC23 IC22 IC21 Reserved IC19 IC18 IC17 IC16 : Type : Default : Type : Default Bits Mnemonic Field Name Explanation Read/Write 31:30 IC23 Interrupt Source Interrupt Source Control 23 (Default: 00) Control 23 These bits specify the active state of PCIPMC interrupts.
Page 459 Chapter 15 Interrupt Controller Bits Mnemonic Field Name Explanation Read/Write Interrupt Source 17:16 IC16 Interrupt Source Control 16 (Default: 00) Control 16 These bits specify the active state of PCIC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 15:14 Interrupt Source Interrupt Source Control 7 (Default: 00)
Page 460: Interrupt Detection Mode Register 1 (Irdm1) 0Xf608
Chapter 15 Interrupt Controller 15.4.3 Interrupt Detection Mode Register 1 (IRDM1) 0xF608 IC31 IC30 IC29 IC28 IC27 IC26 IC25 IC24 : Type : Default IC15 IC14 IC13 IC12 IC11 IC10 : Type : Default Mnemonic Field Name Explanation Read/Write 31:30 IC31 Interrupt Source Interrupt Source Control 31 (Default: 00, R/W)
Page 461 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt Source 19:18 IC25 Interrupt Source Control 25 (Default: 00, R/W) Control 25 These bits specify the active state of ACLCPME interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 17:16 IC24 Interrupt Source...
Page 462 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt Source Interrupt Source Control 9 (Default: 00) Control 9 These bits specify the active state of SIO[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Interrupt Source Control 8 (Default: 00) Control 8 These bits specify the active state of SIO[0] interrupts.
Page 463: Interrupt Level Register 0 (Irlvl0) 0Xf610
Chapter 15 Interrupt Controller 15.4.4 Interrupt Level Register 0 (IRLVL0) 0xF610 Reserved IL17 Reserved IL16 : Type : Default Reserved Reserved : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL17 Interrupt Level 17 Interrupt Level of INT [17] (Default: 000) These bits specify the interrupt level of [TMR [0] 000: Interrupt Level 0 (Interrupt disable)
Page 464 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt Level 0 Interrupt Level of INT [0] (Default: 000) These bits specify the interrupt level of ECC Error interrupts. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5...
Page 465: Interrupt Level Register (Irlvl1) 0Xf614
Chapter 15 Interrupt Controller 15.4.5 Interrupt Level Register (IRLVL1) 0xF614 Reserved IL19 Reserved IL18 : Type : Default Reserved Reserved : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL19 Interrupt Level 19 Interrupt Level of INT [19] (Default: 000) These bits specify the interrupt level of TMR [2].
Page 466 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt Level 2 Interrupt Level of INT [2] (Default: 000) These bits specify the interrupt level of external INT[0]. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5...
Page 467: Interrupt Level Register 2 (Irlvl2) 0Xf618
Chapter 15 Interrupt Controller 15.4.6 Interrupt Level Register 2 (IRLVL2) 0xF618 Reserved IL21 Reserved : Type : Default Reserved Reserved : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL21 Interrupt Level 21 Interrupt Level of INT [21] (Default: 000) These bits specify the interrupt level of NDFMC.
Page 468: Interrupt Level Register 3 (Irlvl3) 0Xf61C
Chapter 15 Interrupt Controller 15.4.7 Interrupt Level Register 3 (IRLVL3) 0xF61C Reserved IL23 Reserved IL22 : Type : Default Reserved Reserved : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL23 Interrupt Level 23 Interrupt Level of INT [23] (Default: 000) These bits specify the interrupt level of PCIPME0 interrupts.
Page 469 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt level 6 Interrupt Level of INT [6] (Default: 000) These bits specify the interrupt level of external INT[4] / ETHERC0. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4...
Page 470: Interrupt Level Register 4 (Irlvl4) 0Xf620
Chapter 15 Interrupt Controller 15.4.8 Interrupt Level Register 4 (IRLVL4) 0xF620 Reserved IL25 Reserved IL24 : Type : Default Reserved Reserved : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL25 Interrupt level 25 Interrupt Level of INT [25] (Default: 000, R/W) These bits specify the interrupt level of ACLCPME interrupts.
Page 471 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt level 8 Interrupt Level of INT [8] (Default: 000) These bits specify the interrupt level of SIO [0] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5...
Page 472: Interrupt Level Register 5 (Irlvl5) 0Xf624
Chapter 15 Interrupt Controller 15.4.9 Interrupt Level Register 5 (IRLVL5) 0xF624 Reserved IL27 Reserved IL26 : Type : Default Reserved IL11 Reserved IL10 : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL27 Interrupt level 27 Interrupt Level of INT [27] (Default: 000) These bits specify the interrupt level of DMA1 [0] interrupts.
Page 473 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write IL10 Interrupt Level 10 Interrupt Level of INT [10] (Default: 000) These bits specify the interrupt level of DMA0 [0] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4...
Page 474: Interrupt Level Register 6 (Irlvl6) 0Xf628
Chapter 15 Interrupt Controller 15.4.10 Interrupt Level Register 6 (IRLVL6) 0xF628 Reserved IL29 Reserved IL28 : Type : Default Reserved IL13 Reserved IL12 : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL29 Interrupt level 29 Interrupt Level of INT [29] (Default: 000) These bits specify the interrupt level of DMA1 [2] interrupts.
Page 475 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write IL12 Interrupt level 12 Interrupt Level of INT [12] (Default: 000) These bits specify the interrupt level of DMA0 [2] interrupts. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4...
Page 476: Interrupt Level Register 7 (Irlvl7) 0Xf62C
Chapter 15 Interrupt Controller 15.4.11 Interrupt Level Register 7 (IRLVL7) 0xF62C Reserved IL31 Reserved IL30 : Type : Default Reserved IL15 Reserved IL14 : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:27 Reserved 26:24 IL31 Interrupt level 31 Interrupt Level of INT [31] (Default: 000) These bits specify the interrupt level of SPI interrupts.
Page 477 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write IL14 Interrupt Level 14 Interrupt Level of INT [14] (Default: 000) These bits specify the interrupt level of IRC interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5...
Page 478: Interrupt Mask Level Register (Irmsk) 0Xf640
Chapter 15 Interrupt Controller 15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 Reserved : Type : Default Reserved : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:3 Reserved Interrupt Mask Interrupt Mask Level (Default: 000) Level These bits specify the interrupt mask level. Masks interrupts with a mask level equal to or lower than the set mask level.
Page 479: Interrupt Edge Detection Clear Register (Iredc) 0Xf660
Chapter 15 Interrupt Controller 15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660 Reserved : Type : Default Reserved Reserved EDCS0 EDCE0 : Type RW1C 0000 : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ 31:9 ⎯ Reserved EDCE0 Edge Detection Edge Detection Clear Enable 0 (Default: 0) R/W1C Clear Enable 0...
Page 480: Interrupt Pending Register (Irpnd) 0Xf680
Chapter 15 Interrupt Controller 15.4.14 Interrupt Pending Register (IRPND) 0xF680 Indicates the status of each interrupt request regardless of the IRLVL 7-0 and IRMSK value. IS31 IS30 IS29 IS28 IS25 IS24 IS23 IS22 IS21 IS19 IS18 IS17 IS16 IS27 IS26 Reserved : Type : Default...
Page 481 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write IS22 Interrupt Status 22 IRINTREQ [22] status This bit indicates the PCIERR error status. 1: Interrupt requests 0: No interrupt requests IS21 Interrupt Status 21 IRINTREQ [21] status This bit indicates the NDFMC interrupt status. 1: Interrupt requests 0: No interrupt requests ⎯...
Page 482 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write Interrupt Status 9 IRINTREQ [9] status This bit indicates the status of SIO [1] interrupts. 1: Interrupt requests 0: No interrupt requests Interrupt Status 8 IRINTREQ [8] status This bit indicates the status of SIO [0] interrupts. 1: Interrupt requests 0: No interrupt requests Interrupt Status 7...
Page 483: Interrupt Current Status Register (Ircs) 0Xf6A0
Chapter 15 Interrupt Controller 15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0 Reserved : Type : Default Reserved Reserved CAUSE : Type 11111 : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ 31:17 ⎯ Reserved Interrupt Flag Interrupt Flag (Default: 1) This bit indicates the interrupt generation status.
Page 484 Chapter 15 Interrupt Controller Mnemonic Field Name Explanation Read/Write CAUSE Interrupt Cause Interrupt Cause (Default: 0x1F) These bits specify the interrupt cause that was reported to the TX49/H3 core. This field becomes undefined if no interrupt request is pending (i.e., the IF bit is set).
Page 485 Chapter 15 Interrupt Controller 15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 Reserved : Type : Default [15] [14] [13] [12] [11] [10] : Type 0x0000 : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:16 Reserved 15:0 PF0 [15:0] Flag 0 Interrupt Request Flag 0 [15:0] (Default: 0x0000) Changes made to this register are reflected in Flag Register 1 also since...
Page 486: Interrupt Request Flag Register 0 (Irflag0) 0Xf510
Chapter 15 Interrupt Controller 15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 Reserved : Type : Default [15] [14] [13] [12] [11] [10] : Type 0x0000 : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:16 Reserved 15:0 PF1 [15:0] Flag 1 Interrupt Request Flag 1 [15:0] (Default: 0x0000) Changes made to this register are reflected in Flag Register 0 also since...
Page 487: Interrupt Request Polarity Control Register (Irpol) 0Xf518
Chapter 15 Interrupt Controller 15.4.18 Interrupt Request Polarity Control Register (IRPOL) 0xF518 Reserved : Type : Default [15] [14] [13] [12] [11] [10] : Type 0x0000 : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:16 Reserved 15:0 FPC [15:0] Flag Polarity Flag Polarity Control [15:0] (Default: 0x0000) Control...
Page 488: Interrupt Request Control Register (Irrcnt) 0Xf51C
Chapter 15 Interrupt Controller 15.4.19 Interrupt Request Control Register (IRRCNT) 0xF51C Reserved : Type : Default Reserved INTPOL EXTPOL R/W : Type : Default Mnemonic Field Name Explanation Read/Write ⎯ ⎯ ⎯ 31:3 Reserved External Interrupt External Interrupt Open Drain Control (Default: 0) OD Control This bit specifies whether to make the external interrupt signal (IRC[2]*) an open drain pin or not.
Page 489: Interrupt Request Internal Interrupt Mask Register (Irmaskint) 0Xf520
Chapter 15 Interrupt Controller 15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520 Reserved : Type : Default MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT [15] [14] [13] [12] [11] [10] : Type 0x0000 : Default...
Page 490: Interrupt Request External Interrupt Mask Register (Irmaskext) 0Xf524
Chapter 15 Interrupt Controller 15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524 Reserved : Type : Default MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT [15] [14] [13] [12] [11] [10] : Type 0x0000 : Default...
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Page 499: Extended Ejtag Interface
Execution control (run, break, step, register/memory access) • Real-time PC tracing Please contact your local Toshiba Sales representative for more information regarding how to connect the emulation probe. The two functions of the Extended EJTAG Interface operate in one of two modes.
Page 500: Jtag Boundary Scan Test
This section explains only those portions that are unique to the TX4937. Please refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for all other portion not covered here. Please contact your local Toshiba Sales representative for more information regarding the required BSDL files when performing the JTAG Boundary Scan Test.
Page 501: Instruction Register
Chapter 20 Extended EJTAG Interface 20.2.2 Instruction Register The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting either one or both of the test to be performed and the Test Data Register to be accessed. The Data Register is selected according to the instruction code in Table 20.2.1.
Page 502 Chapter 20 Extended EJTAG Interface Table 20.2.2 TX4937 Processor JTAG Scan Sequence (1/2) JTAG Scan JTAG Scan JTAG Scan Signal Name Signal Name Signal Name Sequence Sequence Sequence EEPROM_CS PCIAD[20] PIO[2] PCST[3] PCIAD[19] PIO[1] PCST[2] PCIAD[26] BYPASSPLL * PCST[1] PCIAD[31] SD[1] PCST[0] PCIAD[29]...
Page 503 Chapter 20 Extended EJTAG Interface Table 20.2.2 TX4937 Processor JTAG Scan Sequence (2/2) JTAG Scan JTAG Scan JTAG Scan Signal Name Signal Name Signal Name Sequence Sequence Sequence DATA[55] ADDR[8] DATA[38] DATA[54] ADDR[7] DATA[36] DATA[22] ADDR[6] DATA[5] DATA[53] ADDR[5] DATA[34] DATA[23] ADDR[4] DATA[3]...
Page 504: Device Id Register
Chapter 20 Extended EJTAG Interface 20.2.4 Device ID Register The Device ID Register is a 32-bit shift register. This register is used for reading the ID code that expresses the IC manufacturer, part number, and version from the IC and sending it to a serial device. The following figure shows the configuration of the Device ID Register.
Page 505: Initializing The Extended Ejtag Interface
Chapter 20 Extended EJTAG Interface 20.3 Initializing the Extended EJTAG Interface The Extended EJTAG Interface is not reset by asserting the RESET* signal. Operation of the TX49/H3 core is not guaranteed if the Extended EJTAG Interface is not reset. This interface is initialized by either of the following methods.
Page 506 Chapter 20 Extended EJTAG Interface 20-8...
Page 507: Absolute Maximum Rating (*1)
°C (Package Temperature) (*3) A recommended operating condition is a usage condition that Toshiba recommends for a product to function properly and maintain a uniform level of quality. Using a product such that even one item is not under the recommended operating conditions may cause a malfunction to occur. When designing application devices, be sure that these recommended operating conditions ranges are never exceeded.
Page 508: Dc Characteristics Of Pins Other Than Pci Interface Pins
Chapter 21 Electrical Characteristics 21.3 DC characteristics 21.3.1 DC characteristics of pins other than PCI Interface pins = 3.3V ± 0.2V, V = 1.5V ± 0.1V, V (Tc = 0 - 70°C, V = 0V) ddIO CCInt Item Symbol Condition Min.
Page 509: Dc Characteristics Of Pci Interface Pins
Chapter 21 Electrical Characteristics 21.3.2 DC characteristics of PCI Interface pins = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V (Tc = 0 – 70°C, V = 0 V) ddIO ddIN Item Symbol Conditions Min. Max.
Page 510: Pll Power
Chapter 21 Electrical Characteristics 21.4 PLL power 21.4.1 PLL power connection example Place C1, C2, C3, R, and L as close to the TX4937 as possible. TX4937 VddInt VddInt VddPLL2_A VddPLL1_A VssPLL1_A VssPLL2_A Item Symbol Recommended Value Unit Ω Resistance µ...
Page 511: Ac Characteristics
Chapter 21 Electrical Characteristics 21.5 AC characteristics 21.5.1 MASTERCLK AC characteristics = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, VSS = 0 V) (Tc = 0 – 70°C, V CCIO CCInt Item Symbol Conditions Min. Max.
Page 512: Sdram Interface Ac Characteristics
Chapter 21 Electrical Characteristics 21.5.3 SDRAM Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V, CL = 150 pF) Item Symbol Conditions Min. Max.
Page 513 Chapter 21 Electrical Characteristics SDCLK[n] SDCLKIN SU_* HO_* INPUT inputs valid Figure 21.5.4 Timing Diagram: Input Signal when in the Non-bypass Mode (SDCLK Reference) 21-7...
Page 514: External Bus Interface Ac Characteristics
Chapter 21 Electrical Characteristics 21.5.4 External Bus Interface AC characteristics = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V (Tc = 0 – 70°C, V = 0 V) CCIO CCInt Item Symbol Condition Min. Max. Unit ⎯...
Page 515: Pci Interface Ac Characteristics (66 Mhz)
Chapter 21 Electrical Characteristics 21.5.5 PCI Interface AC characteristics (66 MHz) = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V (Tc = 0 – 70°C, V = 0 V) CCIO CCInt Item Symbol Conditions Min. Max.
Page 516 Chapter 21 Electrical Characteristics CYC66 CYC33 HIGH66 HIGH33 LOW66 LOW33 SLEW66 SLEW33 0.6 Vcc 0.5 Vcc 0.4 Vcc p-to-p 0.4 Vcc (minimum) 0.3 Vcc 0.2 Vcc PCICLKIN (Vcc=3.3V) su66 su33 SUPP66 SUPP33 HO66 HO33 HOPP66 HOPP33 INPUT inputs valid VAL66 VAL33 VALPP66 VALPP33...
Page 517: Pci Eeprom Interface Ac Characteristics
Chapter 21 Electrical Characteristics 21.5.7 PCI EEPROM Interface AC characteristics = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Item Symbol Conditions Min. Max. Unit ⎯...
Page 518: Interrupt Interface Ac Characteristics
Chapter 21 Electrical Characteristics Notes: (1) DMAREQ[n] Edge Detection: Set the pulse width to 1.1× the GBUSCLK cycle or higher. Level Detection: There is no AC characteristic definition. Continue asserting DMAREQ[3:0] until DMAACK[3:0] is received. (2) DMAACK[n] The DMAACK[n] signal is synchronous to SDCLK. (It is driven by GUBSCLK inside the chip. See Chapter 6 for more information.) The DMAACK[n] signal is asserted by SYSCLK or SDCLK for 3 cycles or more.
Page 519: Sio Interface Ac Characteristics
Chapter 21 Electrical Characteristics 21.5.10 SIO Interface AC characteristics = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V (Tc = 0 – 70°C, V = 0 V) CCIO CCInt Item Symbol Conditions Min. Max. Unit 4 ×...
Page 520: Pio Interface Ac Characteristics
Chapter 21 Electrical Characteristics 21.5.12 PIO Interface AC characteristics = 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V (Tc = 0 – 70°C, V = 0 V) CCIO CCInt Item Symbol Conditions Min. Max. Unit IMBUSCLK reference (C ⎯...
Page 521: Pinout And Package Information
Chapter 22 Pinout and Package Information 22. Pinout and Package Information 22.1 Pinout Diagram Figure 22.1.1 shows the TX4937 pinout. Table 22.1.1 provides a pin cross reference by pin number. provides a pin cross reference by pin name. Table 22.1.3 provides a pin cross reference for thermal balls. 22-1...
Page 522 Chapter 22 Pinout and Package Information PCIAD PCIAD PCIAD PCIAD PCIAD PCICLK PCICLK PCICLK PCICLK PCICLK PCICLK C_BE[2] [16] [18] [19] [23] [24] PCIAD PCIAD PCIAD IRDY* FRAME* VddIO VddIO VddIO GNT[0]* REQ[0]* GNT[2]* GNT[3]* DATA[63] [17] [20] [25] PCIAD PCIAD PCIAD PCIAD...
Page 523 Chapter 22 Pinout and Package Information MASTERC PCICLKIN DATA[29] DATA[59] DATA[58] DATA[56] DATA[22] DATA[21] VddIO PLL2VSS_ PLL1VSS_ DATA[31] DATA[61] DATA[60] DATA[27] DATA[26] DATA[24] DATA[54] DATA[53] DATA[52] DATA[20] DATA[51] PLL2VDD_ PLL1VDD_ VddIO VddIO DATA[57] DATA[55] DATA[50] VddIO DATA[19] CGRESET VddIN DATA[62] VddIN DATA[28] VddIO...
Page 524 Chapter 22 Pinout and Package Information Table 22.1.1 Pin Cross Reference by Pin Number (1/2) Num- Num- Num- Num- Num- Pin Name Pin Name Pin Name Pin Name Pin Name PIO[1] PCIAD[0] CE[0]* PCIAD[22] GNT[0]* PIO[0] PCIAD[3] VddIN PCIAD[21] PCICLK[1] SWE* PCIAD[6] PCIAD[20]...
Page 525 Chapter 22 Pinout and Package Information Table 22.1.1 Pin Cross Reference by Pin Number (2/2) Num- Num- Num- Num- Num- Pin Name Pin Name Pin Name Pin Name Pin Name DATA[2] VddIO AC21 AE11 ADDR[9] VddIO DQM[0] AC22 DATA[48] AE12 VSS DATA[33] DATA[7] VddIO...
Page 526 Chapter 22 Pinout and Package Information Table 22.1.2 Pin Cross Reference by Pin Name (1/2) Num- Num- Num- Num- Num- Pin Name Pin Name Pin Name Pin Name Pin Name ACE* CE[5]* DATA[30] DMAREQ[1] PCIAD[7] ACK* CE[6]* DATA[31] DMAREQ[2] PCIAD[8] ADDR[0] CE[7]* DATA[32]...
Page 527 Chapter 22 Pinout and Package Information Table 22.1.2 Pin Cross Reference by Pin Name (2/2) Num- Num- Num- Num- Num- Pin Name Pin Name Pin Name Pin Name Pin Name PIO[0] TEST[1]* AE14 VSS VddIO PIO[1] TEST[2]* AE18 VSS VddIO PIO[2] TEST[3]* AE23 VSS...
Page 528 Chapter 22 Pinout and Package Information Table 22.1.3 Pin Cross Reference for Thermal Balls Num- Num- Num- Num- Num- Pin Name Pin Name Pin Name Pin Name Pin Name 22-8...
Page 529: Package Dimensions
Chapter 22 Pinout and Package Information 22.2 Package Dimensions P-BGA484-3535-1.27B9 Unit: mm 22-9...
Page 530 Chapter 22 Pinout and Package Information 22-10...
Page 531: Notes On Use Of Tmpr4937
Chapter 23 Notes on Use of TMPR4937 23. Notes on Use of TMPR4937 23.1 Notes on TX49/H3 Core • Restriction on detect of the Bus errors when a data cycle generated by load instruction. [Restriction] Error notification to the TX49/H3 Core using Bus errors is not enabled or Executing a SYNC instruction immediately after the preceding load instruction.
Page 532 Chapter 23 Notes on Use of TMPR4937 Bus errors occur the following three conditions. (1) When CCFG.TOE of the Chip Configuration Register is set to “1” (Default: 0), G-Bus timeout error detection is enabled, and the following situation results: • A Bus timeout occurs when a G-Bus Bus Master (TX49/H3 Core, DMAC, or PCIC) is reading the G-Bus •...
Page 533: Notes On External Bus Controller
Chapter 23 Notes on Use of TMPR4937 23.2 Notes on External Bus Controller • Output delay of DATA[63:0] depends on the external bus speed set with EBCCRn.SP. For details on it, see 21.5.4 External Bus Interface AC Characteristics. 23.3 Notes on DMA Controller •...
Page 534 Chapter 23 Notes on Use of TMPR4937 In the case only one channel is used, restarting DMS transfer without a reset of FIFO results in a malfunction when the conditions (1) to (3) are satisfied. When two channels are used in a system, the following table shows settings to cause malfunctions. Transfer restarted Ch.
Page 535 Chapter 23 Notes on Use of TMPR4937 – Only one channel performs single transfer (1) Single transfer performed with only one channel Perform either (a) or (b) to prevent a malfunction. (2) Single transfer performed with one channel and burst transfer Perform (b) to prevent a malfunction.
Page 536: Note On Pci Controller
Chapter 23 Notes on Use of TMPR4937 23.4 Note on PCI Controller • Set four target spaces, that are MEM0, MEM1, MEM2 and IO contained in PCI controller, so that address windows are not duplicated. See 10.3.5 Target Access. • We recommend to set 0 to G2PTOCNT.
Page 537 Chapter 23 Notes on Use of TMPR4937 <Conditions> This problem occurs when the following conditions are satisfied. (1) The broken master detection function is enabled (BMCEN=1). The broken master detection function is enabled or disabled with the BMCEN bit of the PCI bus arbiter configuration register (PBACFG).
Page 538 Chapter 23 Notes on Use of TMPR4937 • Note on use of the PCI boot function [Restriction] Don’t perform PCI boot in default setting. [Violation] When performing PCI boot in the default setting, 64 Mbyte memory space that is 0x0_1C00_0000 to 0x0_1FFF_FFFF (physical address, the area a and b in the figure shown below) is assigned to the PCI bus, and not 4 Mbyte memory space that is 0x0_1FC0_0000 to 0x0_1FFF_FFFF (physical address, the area a).
Page 539 Chapter 23 Notes on Use of TMPR4937 • Restriction when Initiator Write by PDMAC and Target Read conflict. [Restriction] Don’t perform Target Read from a register on the G-Bus when the condition is the following <Conditions>. [Violation] When an Initiator Write transaction using PDMAC (PCI Dedicated DMA Controller) mounted in the PCI Controller of the target product and a Target Read transaction to the target product by the a device on the PCI Bus conflict, there are cases when the Target Read data is corrupted.
Page 540: Notes On Serial I/O Port
Chapter 23 Notes on Use of TMPR4937 23.5 Notes on Serial I/O Port • Restrictions on use of the break function in SIO [Restriction] To transmit breaks to TX4937, synchronize breaks to the start bit. Set consecutively the transmit data to Low immediately after the start bit.
Page 541: Parts Number When Ordering
Chapter 24 Parts Number when Ordering 24. Parts Number when Ordering Maximum Operating Parts Number Package Frequency TMPR4937XBG-300 484-pin PBGA 300 MHz TX4937 TMPR4937XBG-333 484-pin PBGA 333 MHz 24-1...
Page 542 Chapter 24 Parts Number when Ordering 24-2...
Page 543: Appendix Atx49/H3 Core Supplement
PRId Register values of the TX4937 TX49/H3 Core are as follows. Processor Revision Identifier Register: 0x0000 2D30 FPU Implementation/Revision Register (FCR0): 0x0000 2D30 These values may be changed at a later date. Please contact the Toshiba Engineering Department for the most recent information. Interrupts Interrupt signalling of the on-chip interrupt controller is reflected in bit IP[2] of the Cause Register in the TX49/H3 Core.
Page 544 Appendix A TX49/H3 Core Supplement...
Page 545 When this pin is used as SDIN[1], pull down by the resister on the board. (Regarding the value of register, please ask the Engineering Department in Toshiba). Table 3.1.9 AC-link Interface Signals Added the following text to the description of the SDIN[0]...
Page 546 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 Figure 5.2.1 Chip Configuration Register (1/3) WDRST WDRST WDREXEN WDREXEN RW1C R/W1C Figure 5.2.1 Chip Configuration Register (1/3) BEOW BEOW RW1C : Type R/W1C : Type : Initial value : Initial value Figure 5.2.1 Chip Configuration Register (1/3) Read/write attribute of the WDRST (Watchdog Reset...
Page 547 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 Figure 5.2.6 G-Bus Arbiter Control Register ⎯ Reserved PRIORITY ARBMD Reserved 5-13 000_001_010_011_100 Reserved PRIORITY PRIORITY 00_01_10 000_001_010_011_100 Figure 6.3.1 Power-On Sequence At least 100 ms (T.B.D) (T.B.D) PLL settling time (T.B.D) PLL settling time...
Page 548 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 Figure 7.3.13 Ready Input Timing (Read Cycle) 7-18 2 clock 2 clocks Latch D Acknowledge Ready Acknowledge Ready Figure 7.3.13 Ready Input Timing (Read Cycle) 7-18 Start Ready Acknowledge Re Start Ready Acknowledge Re...
Page 549 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer 8-13 <DMSAIRn> 8/0/-8 8/0/-8 Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer Added the following note. 8-13 : When DMSAIRn is set to 0, read access from source device is performed only one time per transmission...
Page 550 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 Figure 11.4.7 Baud Rate Control Register Modified the description of the BCLK (Baud Rate Generator Clock) field. 11-22 00: Select prescalar output T0 (IMBUSCLK/2) 00: Select prescalar output T0 (fc/2) 01: Select prescalar output T2 (IMBUSCLK/8) 01: Select prescalar output T2 (fc/8) 10: Select prescalar output T4 (IMBUSCLK/32)
Page 551 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 Modified line 8 of Section 20.3, Initializing the Extended EJTAG Interface The above methods must be performed while the The above methods must be performed while the 20-7 MASTERCLK signal is being input.
Page 552 TMPR4937 Revision History Page Rev 1.1 Manual Changes and Additions to Rev 1.1 23. Notes on Use of TMPR4938 23.1 Notes on External Bus Controller 23.1 Notes on TX49/H3 Core 23.2 Notes on DMA Controller 23.2 Notes on External Bus Controller 23-1 23.3 Note on PCI Controller 23.3...
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