Spi Master Control Register (Spmcr) 0Xf800 - Toshiba TMPR4925 Manual

17.4.1 SPI Master Control Register (SPMCR)
31
15
Reserved
Bits Mnemonic Field Name
⎯
31 : 8 Reserved
7:6 OPMODE Operation Mode
⎯
5:3 Reserved
⎯
2
1 SPSTP SPI Stop
0 BCLR SPI Buffer Clear
Chapter 17 Serial Peripheral Interface
Reserved
8 7
OPMODE
⎯
Operation Mode (Initial value: 01, R/W)
Set operation mode
00: Don't care. Writing this value to the OPMODE bits doesn't change any thing.
01: Configuration mode
10: Active mode (normal operation mode)
11: Reserved
⎯
⎯
This bit is reserved. Don't write "1" to this bit (Initial value: 0, R/W).
SPI Stop (Initial value: 0, R/W)
If this flag is asserted, the module will stop the transferring after the current frame
has been completed. This bit could be set only when the SPI is in active mode.
Setting the SPI in configuration mode will clear this bit.
0: Normal operation
1: Stop after completion of the current transfer
SPI Buffer Clear (Initial value: 0, R/C)
This flag is used to clear the receive and transmit FIFO. The FIFO logic can be
reset by writing a "1" value to this bit. Please wait until the SPI module is idle
(SIDLE = 1) before activating the BCLR bit.
This register will always be read as "0".
Write:
0: Don't care
1: FIFO clear
Figure 17.4.1 SPI Master Control Register
17-9
0xF800
6 5 3
Reserved
R/W
01
Explanation
16
: Type
: Initial value
2 1 0
BCLR
SPSTP
Reserved
R/W R/W R/C : Type
0 0 0 : Initial value