Toshiba TMPR4925 Manual page 310

Bits Mnemonic Field Name
18:16 ReqDP Request D Port
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15 Reserved
14:12 ReqWP Request W Port
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11 Reserved
10:8 ReqXP Request X Port
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7 Reserved
6:4 ReqYP Request Y Port
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3 Reserved
2:0 ReqZP Request Z Port
Figure 10.4.22 PCI Bus Arbiter Request Port Register (2/2)
Request D Port (Initial value: 100, R/W)
Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request D Port
(Master D).
111: Makes the PCI Controller Master D.
110: Reserved
101: Reserved
100: Reserved
011: Makes REQ*[3] Master D.
010: Makes REQ*[2] Master D.
001: Makes REQ*[1] Master D.
000: Makes REQ*[0] Master D.
Request W Port (Initial value: 011, R/W)
Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request W Port
(Master W).
111: Makes the PCI Controller Master W.
110: Reserved
101: Reserved
100: Reserved
011: Makes REQ*[3] Master W.
010: Makes REQ*[2] Master W.
001: Makes REQ*[1] Master W.
000: Makes REQ*[0] Master W.
Request X Port (Initial value: 010, R/W)
Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request X Port
(Port X).
111: Makes the PCI Controller Master X.
110: Reserved
101: Reserved
100: Reserved
011: Makes REQ*[3] Master X.
010: Makes REQ*[2] Master X.
001: Makes REQ*[1] Master X.
000: Makes REQ*[0] Master X.
Request Y Port (Initial value: 001, R/W)
Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request Y Port
(Port Y).
111: Makes the PCI Controller Master Y.
110: Reserved
101: Reserved
100: Reserved
011: Makes REQ*[3] Master Y.
010: Makes REQ*[2] Master Y.
001: Makes REQ*[1] Master Y.
000: Makes REQ*[0] Master Y.
Request Z Port (Initial value: 000, R/W)
Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request Z Port
(Port Z).
111: Makes the PCI Controller Master Z.
110: Reserved
101: Reserved
100: Reserved
011: Makes REQ*[3] Master Z.
010: Makes REQ*[2] Master Z.
001: Makes REQ*[1] Master Z.
000: Makes REQ*[0] Master Z.
10-50
Chapter 10 PCI Controller
Description
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