Pci Configuration 1 Register (Pcicfg1) 0Xd00C - Toshiba TMPR4925 Manual

10.4.4 PCI Configuration 1 Register (PCICFG1)
The following fields correspond to the following registers.
BIST field → BIST Register of the PCI Configuration Space
Header Type field → Header Type Register in the PCI Configuration Space
Latency Timer field → Latency Timer Register of the PCI Configuration Space
Cache Line Size field → Cache Line Size Register of the PCI Configuration Space.
This register cannot be accessed when the PCI Controller is in the Satellite mode.
31 30
BISTC Reserved
R
0
15
LT
R/W
0x00
Bits Mnemonic Field Name
31 BISTC BIST Capable
⎯
30:24 Reserved
23 MFUNS Multi-Function
22:16 HT Header Type
15:8 LT Latency Timer
7:0 CLS Cache Line Size
24 23
MFUNS
R
0
8 7
BIST Capable (Fixed value: 0, R)
Indicates that the BIST function is not being supported.
Multi-Function (Fixed value: 0, R)
0: Indicates that the device is a single-function device.
Header Type (Initial value: 0x00, R/L)
Indicates the Header type.
0000000: Header Type 0
It is possible to change to the value that was written to the PCICDATA3 Register
when PCICCFG.LCFG is "1".
Latency Timer (Initial value: 0x00, R/W)
Sets the latency timer value. Specifies the PCI Bus clock count during which to abort
access when the GNT* signal is deasserted during PCI access. Since the lower two
bits are fixed to "0", cycle counts can only be specified in multiples of 4.
Cache Line Size (Initial value: 0x00, R/W)
Is used to select the PCI Bus command during a Burst Read transaction. See "10.3.3
Supported PCI Bus Commands)" for more information.
Figure 10.4.4 PCI Configuration 1 Register
10-30
Chapter 10 PCI Controller
0xD00C
22
HT
R/L
0x00
CLS
R/W
0x00
Description
⎯
16
: Type
: Initial value
0
: Type
: Initial value