Toshiba TMPR4925 Manual page 288

Bits Mnemonic Field Name
24 MDPE Master Data
Parity Error
23 FBBCP Fast Back-to-
Back Capable
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22 Reserved
21 66MCP 66 MHz Capable
20 CL Capabilities List
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19:10 Reserved
9 FBBEN Fast Back-to-
Back Enable
8 SEREN SERR* Enable
7 STPC Stepping Control
6 PEREN Parity Error
Response
5 VPS VGA Palette
Snoop
4 MWIEN Memory Write
and Invalidate
Enable
3 SC Special Cycles
2 BM Bus Master
1 MEMSP Memory Space
0 IOSP I/O Space
Master Data Parity Error (Initial value: 0, R/W1C)
Indicates the a parity error occurred when the PCI Controller is the PCI initiator.
This bit is not set when the PCI Controller is the target.
This bit is set when all of the three following conditions are met.
•
It has been detected that the PERR* signal was set either directly or indirectly.
•
The PCI Controller is the Bus Master for a PCI Bus transaction during which
an error occurred.
•
The Parity Error Response bit of the PCI Status Command Register
(PCISTATUS.PEREN) has been set.
Fast Back-to-Back Capable (Fixed value: 1, R)
Indicates whether target access of a fast back-to-back transaction can be accepted.
Is fixed to "1".
66 MHz Capable (Fixed value: 0, R)
Indicates the 66 MHz operation is impossible. Is fixed to "0".
Capabilities List (Fixed value: 1, R)
Indicates that the capabilities list is being implemented. Is fixed to "1".
Fast Back-to-Back Enable (Initial value: 0, R/W)
Indicates that issuing of fast back-to-back transactions has been enabled.
1: Enable
0: Disable
SERR* Enable (Initial value: 0, R/W)
Enables/Disables the SERR* signal.
The SERR* signal reports that either a PCI Bus address parity error or a special
cycle data parity error was detected. The SERR* signal is only asserted when the
Parity Error Response bit is set and this bit is set.
1: Enable
0: Disable
Stepping Control (Fixed value: 0, R)
Indicates that stepping control is not being supported.
Parity Error Response (Initial value: 0, R/W)
Sets operation when a PCI address/data parity error is detected.
A parity error response (either when the Parity Error Response bit
(PCISTATUS.PEREN) of the PERR* Signal Assert or PCI Status, Command
Register is set, or the SERR* signal is asserted) is performed only when this bit is
set.
When this bit is cleared, the PCI Controller ignores all parity errors and continues
the transaction process as if the parity of that transaction was correct.
1: Parity error response is performed.
0: Parity error response is not performed.
VGA Palette Snoop (Fixed value: 0, R)
Indicates that the VGA palette snoop function is not supported.
Memory Write and Invalidate Enable (Initial value: 0, R/W)
Controls whether to use the Memory Write and Invalidate command instead of the
Memory Write command when the PCI Controller is the initiator.
Special Cycles (Fixed value: 0, R)
Indicates that special cycles will not be accepted as PCI targets.
Bus Master (Initial value: 0/1, R/W)
The default is only "1" when in the PCI Boot mode and in the Host mode.
1: Operates as the Bus Master.
0: Does not operate as the Bus Master.
Memory Space (Initial value: 0, R/W)
1: Respond to PCI memory access.
0: Do not respond to PCI memory access.
I/O Space (Initial value: 0, R/W)
1: Respond to PCI I/O access.
0: Do not respond to PCI I/O access.
Figure 10.4.2 PCI Status, Command Register (2/2)
10-28
Chapter 10 PCI Controller
Explanation
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