Dma/Interrupt Control Register 0 (Sidicr0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (Sidicr1) 0Xf404 (Ch. 1) - Toshiba TMPR4925 Manual

11.4.2 DMA/Interrupt Control Register 0 (SIDICR0)
DMA/Interrupt Control Register 1 (SIDICR1)
These registers use either DMA or interrupts to execute the Host Interface.
31
15 14 13 12
TDE RDE TIE RIE SPIE
R/W R/W R/W R/W
0 0 0 0
Bits Mnemonic Field Name
⎯
31:16 Reserved
15 TDE Transmit DMA
Transfer Enable
14 RDE Receive DMA
Transfer Enable
13 TIE Transmit Data
Empty Interrupt
Enable
12 RIE Reception Data
Full Interrupt
Enable
11 SPIE Reception Error
Interrupt Enable
10:9 CTSAC CTSS Active
Condition
⎯
8:6 Reserved
0
11 10 9 8
CTSAC
R/W R/W
0 00
Transmit DMA Enable (Initial value: 0, R/W)
This field sets whether to use DMA in the method for writing transmission data to
the Transmit FIFO.
0: Do not use DMA.
1: Use DMA.
Receive DMA Enable (Initial value: 0, R/W)
This field sets whether to use DMA in the method for reading reception data from
the Receive FIFO.
0: Do not use DMA.
1: Use DMA.
Transmit Data Empty Interrupt Enable (Initial value: 0, R/W)
When there is open space in the Transmit FIFO, this field sets whether to signal an
interrupt. Set "0" when in the DMA Transmit mode (TDE = 1).
0: Do not signal an interrupt when there is open space in the Transmit FIFO.
1: Signal an interrupt when there is open space in the Transmit FIFO.
Receive Data Full Interrupt Enable (Initial value: 0, R/W)
This field sets whether to signal interrupts when reception data is full
(SIDISRn.RDIS = 1) or a reception time out (SIDISRn.TOUT = 1) occurs. Set to "0"
when in the DMA Receive mode (RDE = 1).
0: Do not signal interrupts when reception data is full/reception time out occurred.
1: Signal interrupts when reception data is full/reception time out occurred.
Receive Data Error Interrupt Enable (Initial value: 0, R/W)
This field sets whether to signal interrupts when a reception error (Frame Error,
Parity Error, Overrun Error) occurs (SIDISR.ERI = 1).
0: Do not signal reception error interrupts.
1: Signal reception error interrupts.
CTSS Active Condition (Initial value: 00, R/W)
This field specifies status change interrupt request conditions using the CTS Status
(CTSS) of the Status Change Interrupt Status Register.
00: Do not detect CTS signal changes.
01: Rising edge of the CTS pin
10: Falling edge of the CTS pin
11: Both edges of the CTS pin
Figure 11.4.2 DMA/Interrupt Control Register (1/2)
11-15
Chapter 11 Serial I/O Port
0xF304 (Ch. 0)
0xF404 (Ch. 1)
6 5
0
Description
⎯
⎯
16
: Type
: Initial value
0
STIE
R/W : Type
000000 : Initial value