0Xb044 (Ch. 2) 0Xb064 (Ch. 3) - Toshiba TMPR4925 Manual

8.4.4 DMA Source Address Register (DMSARn)
31
15
Bits Mnemonic Field Name
31:0 SADDR Source Address
SADDR[31:16]
R/W
-
SADDR[15:0]
R/W
-
Source Address (Initial value: undefined, R/W)
This field sets the physical address of the transfer source during Dual Address
transfer. This field sets the physical address of memory access during Single
Address transfer. This field is used for either Memory-to-I/O or I/O-to-Memory
transfers.
Refer to "8.3.7.1 Channel Register Settings During Single Address Transfer" and
"8.3.8.1 Channel Register Settings During Dual Address Transfer" for more
information.
During Burst transfer, the value changes once for each bus operation only by the size
that was transferred. During Single transfer, the value only changes by the value
specified by the DMA Source Address Increment Register (DMSAIRn).
Figure 8.4.4 DMA Source Address Register
8-30
Chapter 8 DMA Controller
0xB004 (ch. 0) 0xB024 (ch. 1)
0xB044 (ch. 2) 0xB064 (ch. 3)
Description
16
: Type
: Initial value
0
: Type
: Initial value