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22.5.6
DMA Interface AC Characteristics...................................................................................................... 22-8
22.5.7
Interrupt Interface AC Characteristics............................................................................................... 22-10
22.5.8
SIO Interface AC Characteristics ...................................................................................................... 22-10
22.5.9
Timer Interface AC Characteristics ....................................................................................................22-11
22.5.10 PIO Interface AC Characteristics .......................................................................................................22-11
22.5.11 AC-link Interface AC Characteristics................................................................................................ 22-12
22.5.12 NAND Flash Memory Interface AC Characteristics ......................................................................... 22-13
22.5.13 CHI Interface AC Characteristics...................................................................................................... 22-14
22.5.14 SPI Interface AC Characteristics ....................................................................................................... 22-15
23. Pin Layout, Package ............................................................................................................................................. 23-1
23.1
Pin Layout.................................................................................................................................................... 23-1
23.2
Package ........................................................................................................................................................ 23-6
24. Usage Notes.......................................................................................................................................................... 24-1
24.1
Limitation on DMA Data Chaining.............................................................................................................. 24-1
24.2
Limitation on a Register Read After an SIO Software Reset ....................................................................... 24-1
24.3
Other Precautions......................................................................................................................................... 24-1
A.1
Processor ID.................................................................................................................................................. A-1
A.2
Interrupts....................................................................................................................................................... A-1
A.3
Bus Snoop ..................................................................................................................................................... A-1
A.4
Halt/Doze Mode............................................................................................................................................ A-1
A.5
Memory Access Order .................................................................................................................................. A-1
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