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22.5.4
External Bus Interface AC Characteristics
Parameter
SYSCLK Cycle Time
SYSCLK HighTime
SYSCLK LowTime
ADDR[19:5] Output delay
CE[5:0]* Output delay
OE* Output delay
SWE* Output delay
BWE[3:0]* Output delay
UAE Output delay
BUSSPRT* Output delay
->
DATA[31:0] Output delay (H
L, L
DATA[31:0] Output delay (High-Z
->
DATA[31:0] Output delay (Valid
DATA[31:0] Input set-up time
DATA[31:0] Input set-up time
->
->
ACK* Output delay (H
L, L
H)
->
ACK* Output delay (High-Z
Valid)
->
ACK* Output delay (Valid
High-Z)
ACK* Input set-up time
ACK* Input hold time
SYSCLK
OUTPUT
INPUT
Figure 22.5.5 Timing Diagrams: External Bus Interface
(Tc = 0 ~ 70°C, V
CCIO
Symbol
t
CYC_SYSCLK
t
HIGH_SYSCLK
t
LOW_SYSCLK
t
VAL_ADDR2
t
VAL_CE
t
VAL_OE
t
VAL_SWE
t
VAL_BWE
t
VAL_UAE
t
VAL_DQM
->
H)
t
VAL_BUS
->
Valid)
t
VAL_DATA2ZV
High-Z)
t
VAL_DATA2VZ
t
SU_DATA2
t
HO_DATA2
t
VAL_ACK
t
VAL_ACKZV
t
VAL_ACKVZ
t
SU_ACK
t
HO_ACK
t
HIGH_SYSCLK
t
VAL_*
t
t
SU_*
HO_*
inputs valid
22-6
Chapter 22 Electrical Characteristics
= 3.3 V ± 0.3 V, V
= 1.5 V ± 0.1 V, V
CCInt
Rating
t
CYC_SYSCLK
t
LOW_SYSCLK
outputs valid
= 0 V)
SS
Min.
Max.
Unit
⎯
12.5
ns
⎯
4
ns
⎯
4
ns
1.5
9.5
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
⎯
6.0
ns
⎯
1.0
ns
1.5
9.0
ns
1.5
9.0
ns
1.5
9.0
ns
⎯
6.0
ns
⎯
0.5
ns
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